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[80.15.154.113]) by smtp.googlemail.com with ESMTPSA id c85sm2789756wmd.0.2016.04.19.06.39.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Apr 2016 06:39:55 -0700 (PDT) From: Alvise Rigo To: qemu-devel@nongnu.org, mttcg@listserver.greensocs.com Date: Tue, 19 Apr 2016 15:39:30 +0200 Message-Id: <1461073171-22953-14-git-send-email-a.rigo@virtualopensystems.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1461073171-22953-1-git-send-email-a.rigo@virtualopensystems.com> References: <1461073171-22953-1-git-send-email-a.rigo@virtualopensystems.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [RFC v8 13/14] target-arm: cpu64: use custom set_excl hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , claudio.fontana@huawei.com, Alvise Rigo , "open list:ARM" , serge.fdrv@gmail.com, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, alex.bennee@linaro.org, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In aarch64 the LDXP/STXP instructions allow to perform up to 128 bits exclusive accesses. However, due to a softmmu limitation, such wide accesses are not allowed. To workaround this limitation, we need to support LoadLink instructions that cover at least 128 consecutive bits (see the next patch for more details). Suggested-by: Jani Kokkonen Suggested-by: Claudio Fontana Signed-off-by: Alvise Rigo --- target-arm/cpu64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index cc177bb..1d45e66 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -287,6 +287,13 @@ static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) } } +static void aarch64_set_excl_range(CPUState *cpu, hwaddr addr, hwaddr size) +{ + cpu->excl_protected_range.begin = addr; + /* At least cover 128 bits for a STXP access (two paired doublewords case)*/ + cpu->excl_protected_range.end = addr + 16; +} + static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); @@ -297,6 +304,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs = 34; cc->gdb_core_xml_file = "aarch64-core.xml"; + cc->cpu_set_excl_protected_range = aarch64_set_excl_range; } static void aarch64_cpu_register(const ARMCPUInfo *info)