From patchwork Fri Apr 15 03:31:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Xu X-Patchwork-Id: 610742 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qmNdx6cLLz9sBc for ; Fri, 15 Apr 2016 13:42:29 +1000 (AEST) Received: from localhost ([::1]:53036 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aqueK-0006cx-71 for incoming@patchwork.ozlabs.org; Thu, 14 Apr 2016 23:42:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aquUi-0004Fu-TN for qemu-devel@nongnu.org; Thu, 14 Apr 2016 23:32:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aquUf-000456-N7 for qemu-devel@nongnu.org; Thu, 14 Apr 2016 23:32:32 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55134) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aquUf-00044p-GJ for qemu-devel@nongnu.org; Thu, 14 Apr 2016 23:32:29 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2A24681104; Fri, 15 Apr 2016 03:32:29 +0000 (UTC) Received: from pxdev.xzpeter.org.com (vpn1-4-123.pek2.redhat.com [10.72.4.123]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u3F3VgW7002504; Thu, 14 Apr 2016 23:32:17 -0400 From: Peter Xu To: qemu-devel@nongnu.org Date: Fri, 15 Apr 2016 11:31:29 +0800 Message-Id: <1460691099-3024-4-git-send-email-peterx@redhat.com> In-Reply-To: <1460691099-3024-1-git-send-email-peterx@redhat.com> References: <1460691099-3024-1-git-send-email-peterx@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v3 03/13] acpi: add DMAR scope definition for root IOAPIC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, rkrcmar@redhat.com, peterx@redhat.com, alex.williamson@redhat.com, jan.kiszka@web.de, wexu@redhat.com, pbonzini@redhat.com, marcel@redhat.com, imammedo@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" To enable interrupt remapping for intel IOMMU device, each IOAPIC device in the system reported via ACPI MADT must be explicitly enumerated under one specific remapping hardware unit. This patch adds the root-complex IOAPIC into the default DMAR device. Please refer to VT-d spec 8.3.1.1 for more information. Signed-off-by: Peter Xu --- hw/i386/acpi-build.c | 17 +++++++++++++++-- include/hw/acpi/acpi-defs.h | 15 +++++++++++++++ include/hw/pci-host/q35.h | 9 +++++++++ 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 80dd1bb..5d2d87b 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -77,6 +77,9 @@ #define ACPI_BUILD_DPRINTF(fmt, ...) #endif +/* Default IOAPIC ID */ +#define ACPI_BUILD_IOAPIC_ID 0x0 + typedef struct AcpiMcfgInfo { uint64_t mcfg_base; uint32_t mcfg_size; @@ -375,7 +378,6 @@ build_madt(GArray *table_data, GArray *linker, PCMachineState *pcms) io_apic = acpi_data_push(table_data, sizeof *io_apic); io_apic->type = ACPI_APIC_IO; io_apic->length = sizeof(*io_apic); -#define ACPI_BUILD_IOAPIC_ID 0x0 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID; io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); io_apic->interrupt = cpu_to_le32(0); @@ -2582,6 +2584,9 @@ build_dmar_q35(MachineState *ms, GArray *table_data, GArray *linker) AcpiTableDmar *dmar; AcpiDmarHardwareUnit *drhd; uint8_t dmar_flags = 0; + AcpiDmarDeviceScope *scope = NULL; + /* Root complex IOAPIC use one path[0] only */ + uint16_t scope_size = sizeof(*scope) + sizeof(uint16_t); if (ms->iommu_intr) { /* enable INTR for the IOMMU device */ @@ -2595,11 +2600,19 @@ build_dmar_q35(MachineState *ms, GArray *table_data, GArray *linker) /* DMAR Remapping Hardware Unit Definition structure */ drhd = acpi_data_push(table_data, sizeof(*drhd)); drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); - drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */ + drhd->length = cpu_to_le16(sizeof(*drhd) + scope_size); drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL; drhd->pci_segment = cpu_to_le16(0); drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); + /* Scope definition for the root-complex IOAPIC */ + scope = acpi_data_push(table_data, scope_size); + scope->entry_type = cpu_to_le16(ACPI_DMAR_DEV_SCOPE_TYPE_IOAPIC); + scope->length = scope_size; + scope->enumeration_id = cpu_to_le16(ACPI_BUILD_IOAPIC_ID); + scope->bus = cpu_to_le16(Q35_PSEUDO_BUS_PLATFORM); + scope->path[0] = cpu_to_le16(Q35_PSEUDO_DEVFN_IOAPIC); + build_header(linker, table_data, (void *)(table_data->data + dmar_start), "DMAR", table_data->len - dmar_start, 1, NULL, NULL); } diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index c7a03d4..2430af6 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -556,6 +556,20 @@ enum { /* * Sub-structures for DMAR */ + +#define ACPI_DMAR_DEV_SCOPE_TYPE_IOAPIC (0x03) + +/* Device scope structure for DRHD. */ +struct AcpiDmarDeviceScope { + uint8_t entry_type; + uint8_t length; + uint16_t reserved; + uint8_t enumeration_id; + uint8_t bus; + uint16_t path[0]; /* list of dev:func pairs */ +} QEMU_PACKED; +typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope; + /* Type 0: Hardware Unit Definition */ struct AcpiDmarHardwareUnit { uint16_t type; @@ -564,6 +578,7 @@ struct AcpiDmarHardwareUnit { uint8_t reserved; uint16_t pci_segment; /* The PCI Segment associated with this unit */ uint64_t address; /* Base address of remapping hardware register-set */ + AcpiDmarDeviceScope scope[0]; } QEMU_PACKED; typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit; diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index c5c073d..9afc221 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -175,4 +175,13 @@ typedef struct Q35PCIHost { uint64_t mch_mcfg_base(void); +/* + * Arbitary but unique BNF number for IOAPIC device. This is only + * used when interrupt remapping is enabled. + * + * TODO: make sure there would have no conflict with real PCI bus + */ +#define Q35_PSEUDO_BUS_PLATFORM (0xff) +#define Q35_PSEUDO_DEVFN_IOAPIC (0x00) + #endif /* HW_Q35_H */