From patchwork Mon Jan 4 18:52:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Guangrong X-Patchwork-Id: 562660 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 75BBC1402C0 for ; Tue, 5 Jan 2016 05:59:52 +1100 (AEDT) Received: from localhost ([::1]:46718 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aGAMA-0005HO-Fd for incoming@patchwork.ozlabs.org; Mon, 04 Jan 2016 13:59:50 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56059) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aGALg-0004RD-6i for qemu-devel@nongnu.org; Mon, 04 Jan 2016 13:59:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aGALb-0000Ud-Ls for qemu-devel@nongnu.org; Mon, 04 Jan 2016 13:59:20 -0500 Received: from mga14.intel.com ([192.55.52.115]:40691) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aGALb-0000UK-BZ for qemu-devel@nongnu.org; Mon, 04 Jan 2016 13:59:15 -0500 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 04 Jan 2016 10:59:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,521,1444719600"; d="scan'208";a="853359639" Received: from xiaoreal1.sh.intel.com (HELO xiaoreal1.sh.intel.com.sh.intel.com) ([10.239.48.79]) by orsmga001.jf.intel.com with ESMTP; 04 Jan 2016 10:59:14 -0800 From: Xiao Guangrong To: pbonzini@redhat.com, imammedo@redhat.com Date: Tue, 5 Jan 2016 02:52:03 +0800 Message-Id: <1451933528-133684-2-git-send-email-guangrong.xiao@linux.intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1451933528-133684-1-git-send-email-guangrong.xiao@linux.intel.com> References: <1451933528-133684-1-git-send-email-guangrong.xiao@linux.intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.115 Cc: Xiao Guangrong , ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, gleb@kernel.org, mtosatti@redhat.com, qemu-devel@nongnu.org, stefanha@redhat.com, dan.j.williams@intel.com, rth@twiddle.net Subject: [Qemu-devel] [PATCH 1/6] pc: acpi: bump DSDT/SSDT compliance revision to v2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Igor Mammedov It turns on 64-bit integer handling in OSPM, which will be used for writing simpler/smaller AML code in following patch. Tested with Windows XP and Windows Server 2008, Linux: * XP doesn't care about revision and continues to use 32 integers and boots just fine with this change. * WS 2008 and Linux - support rev2 and use 64-bit integers [ Xiao: make dsdt/ssdt be v1 in qemu version <= 2.5 to keep compatible. ] Signed-off-by: Igor Mammedov Signed-off-by: Xiao Guangrong --- hw/acpi/ich9.c | 32 ++++++++++++++++++++++++++++++++ hw/acpi/nvdimm.c | 10 ++++++---- hw/acpi/piix4.c | 3 +++ hw/i386/acpi-build.c | 24 +++++++++++++++++------- include/hw/acpi/ich9.h | 2 ++ include/hw/i386/pc.h | 14 +++++++++++++- include/hw/mem/nvdimm.h | 2 +- 7 files changed, 74 insertions(+), 13 deletions(-) diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 1c7fcfa..b26f4cc 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -400,6 +400,33 @@ static void ich9_pm_set_enable_tco(Object *obj, bool value, Error **errp) s->pm.enable_tco = value; } +static void ich9_pm_get_dsdt_revision(Object *obj, Visitor *v, + void *opaque, const char *name, + Error **errp) +{ + ICH9LPCPMRegs *pm = opaque; + uint8_t value = pm->dsdt_revision; + + visit_type_uint8(v, &value, name, errp); +} + +static void ich9_pm_set_dsdt_revision(Object *obj, Visitor *v, + void *opaque, const char *name, + Error **errp) +{ + ICH9LPCPMRegs *pm = opaque; + Error *local_err = NULL; + uint8_t value; + + visit_type_uint8(v, &value, name, &local_err); + if (local_err) { + goto out; + } + pm->dsdt_revision = value; +out: + error_propagate(errp, local_err); +} + void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp) { static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN; @@ -407,6 +434,7 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp) pm->disable_s3 = 0; pm->disable_s4 = 0; pm->s4_val = 2; + pm->dsdt_revision = 2; object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE, &pm->pm_io_base, errp); @@ -435,6 +463,10 @@ void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp) ich9_pm_get_enable_tco, ich9_pm_set_enable_tco, NULL); + object_property_add(obj, ACPI_DSDT_REVISION, "uint8", + ich9_pm_get_dsdt_revision, + ich9_pm_set_dsdt_revision, + NULL, pm, NULL); } void ich9_pm_device_plug_cb(ICH9LPCPMRegs *pm, DeviceState *dev, Error **errp) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 9534418..a2c58dd 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -430,7 +430,8 @@ static void nvdimm_build_nvdimm_devices(GSList *device_list, Aml *root_dev) } static void nvdimm_build_ssdt(GSList *device_list, GArray *table_offsets, - GArray *table_data, GArray *linker) + GArray *table_data, GArray *linker, + uint8_t revision) { Aml *ssdt, *sb_scope, *dev; @@ -468,12 +469,12 @@ static void nvdimm_build_ssdt(GSList *device_list, GArray *table_offsets, g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); build_header(linker, table_data, (void *)(table_data->data + table_data->len - ssdt->buf->len), - "SSDT", ssdt->buf->len, 1, "NVDIMM"); + "SSDT", ssdt->buf->len, revision, "NVDIMM"); free_aml_allocator(); } void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, - GArray *linker) + GArray *linker, uint8_t revision) { GSList *device_list; @@ -483,6 +484,7 @@ void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, return; } nvdimm_build_nfit(device_list, table_offsets, table_data, linker); - nvdimm_build_ssdt(device_list, table_offsets, table_data, linker); + nvdimm_build_ssdt(device_list, table_offsets, table_data, linker, + revision); g_slist_free(device_list); } diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 2cd2fee..9d365f8 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -83,6 +83,8 @@ typedef struct PIIX4PMState { uint8_t disable_s4; uint8_t s4_val; + uint8_t dsdt_revision; + AcpiCpuHotplug gpe_cpu; MemHotplugState acpi_memory_hotplug; @@ -588,6 +590,7 @@ static Property piix4_pm_properties[] = { DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0), DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0), DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2), + DEFINE_PROP_UINT8(ACPI_DSDT_REVISION, PIIX4PMState, dsdt_revision, 2), DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState, use_acpi_pci_hotplug, true), DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 4cc1440..4674461 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -95,6 +95,7 @@ typedef struct AcpiPmInfo { uint16_t sci_int; uint8_t acpi_enable_cmd; uint8_t acpi_disable_cmd; + uint8_t dsdt_revision; uint32_t gpe0_blk; uint32_t gpe0_blk_len; uint32_t io_base; @@ -213,6 +214,13 @@ static void acpi_get_pm_info(AcpiPmInfo *pm) pm->s4_val = false; } qobject_decref(o); + o = object_property_get_qobject(obj, ACPI_DSDT_REVISION, NULL); + if (o) { + pm->dsdt_revision = qint_get_int(qobject_to_qint(o)); + } else { + pm->dsdt_revision = 0x1; + } + qobject_decref(o); /* Fill in mandatory properties */ pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL); @@ -932,7 +940,7 @@ static Aml *build_crs(PCIHostState *host, static void build_ssdt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc, - PcPciInfo *pci, PcGuestInfo *guest_info) + PcPciInfo *pci, PcGuestInfo *guest_info, uint8_t revision) { MachineState *machine = MACHINE(qdev_get_machine()); uint32_t nr_mem = machine->ram_slots; @@ -1378,7 +1386,7 @@ build_ssdt(GArray *table_data, GArray *linker, g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); build_header(linker, table_data, (void *)(table_data->data + table_data->len - ssdt->buf->len), - "SSDT", ssdt->buf->len, 1, NULL); + "SSDT", ssdt->buf->len, revision, NULL); free_aml_allocator(); } @@ -1605,7 +1613,8 @@ build_dmar_q35(GArray *table_data, GArray *linker) } static void -build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) +build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc, + uint8_t revision) { AcpiTableHeader *dsdt; @@ -1616,7 +1625,7 @@ build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc) memset(dsdt, 0, sizeof *dsdt); build_header(linker, table_data, dsdt, "DSDT", - misc->dsdt_size, 1, NULL); + misc->dsdt_size, revision, NULL); } static GArray * @@ -1732,7 +1741,7 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) /* DSDT is pointed to by FADT */ dsdt = tables_blob->len; - build_dsdt(tables_blob, tables->linker, &misc); + build_dsdt(tables_blob, tables->linker, &misc, pm.dsdt_revision); /* Count the size of the DSDT and SSDT, we will need it for legacy * sizing of ACPI tables. @@ -1746,7 +1755,7 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) ssdt = tables_blob->len; acpi_add_table(table_offsets, tables_blob); build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, - guest_info); + guest_info, pm.dsdt_revision); aml_len += tables_blob->len - ssdt; acpi_add_table(table_offsets, tables_blob); @@ -1779,7 +1788,8 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables) } if (acpi_has_nvdimm()) { - nvdimm_build_acpi(table_offsets, tables_blob, tables->linker); + nvdimm_build_acpi(table_offsets, tables_blob, tables->linker, + pm.dsdt_revision); } /* Add tables supplied by user (if any) */ diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index 345fd8d..fa51e69 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -56,6 +56,8 @@ typedef struct ICH9LPCPMRegs { uint8_t disable_s4; uint8_t s4_val; uint8_t smm_enabled; + uint8_t dsdt_revision; + bool enable_tco; TCOIORegs tco_regs; } ICH9LPCPMRegs; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index b0d6283..3b934be 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -148,6 +148,8 @@ typedef struct PcPciInfo { #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len" #define ACPI_PM_PROP_TCO_ENABLED "enable_tco" +#define ACPI_DSDT_REVISION "dsdt_revision" + struct PcGuestInfo { bool isapc_ram_fw; hwaddr ram_size, ram_size_below_4g; @@ -353,7 +355,17 @@ int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); #define PC_COMPAT_2_5 \ - HW_COMPAT_2_5 + HW_COMPAT_2_5 \ + {\ + .driver = "PIIX4_PM",\ + .property = ACPI_DSDT_REVISION,\ + .value = stringify(1),\ + },\ + {\ + .driver = "ICH9-LPC",\ + .property = ACPI_DSDT_REVISION,\ + .value = stringify(1),\ + }, #define PC_COMPAT_2_4 \ PC_COMPAT_2_5 \ diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index 49183c1..fd2af14 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -28,5 +28,5 @@ #define TYPE_NVDIMM "nvdimm" void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data, - GArray *linker); + GArray *linker, uint8_t revision); #endif