From patchwork Sat Jan 2 22:25:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 562108 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C6A551409C3 for ; Sun, 3 Jan 2016 09:26:03 +1100 (AEDT) Received: from localhost ([::1]:39927 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aFUcb-00059Q-KI for incoming@patchwork.ozlabs.org; Sat, 02 Jan 2016 17:26:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53155) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aFUcI-0004dK-FB for qemu-devel@nongnu.org; Sat, 02 Jan 2016 17:25:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aFUcF-0006tu-4J for qemu-devel@nongnu.org; Sat, 02 Jan 2016 17:25:42 -0500 Received: from out1134-218.mail.aliyun.com ([42.120.134.218]:28040) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aFUcE-0006tR-PZ for qemu-devel@nongnu.org; Sat, 02 Jan 2016 17:25:39 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.08846903|-1; FP=0|0|0|0|0|-1|-1|-1; HT=e01l04444; MF=chengang@emindsoft.com.cn; NM=1; PH=DS; RN=6; RT=5; SR=0; TI=SMTPD_----4PYISBK_1451773529; Received: from localhost.localdomain.localdomain(mailfrom:chengang@emindsoft.com.cn ip:223.72.67.13) by smtp.aliyun-inc.com(10.147.39.32); Sun, 03 Jan 2016 06:25:29 +0800 From: chengang@emindsoft.com.cn To: peter.maydell@linaro.org, rth@twiddle.net, cmetcalf@ezchip.com Date: Sun, 3 Jan 2016 06:25:15 +0800 Message-Id: <1451773519-10134-2-git-send-email-chengang@emindsoft.com.cn> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1451773519-10134-1-git-send-email-chengang@emindsoft.com.cn> References: <1451773519-10134-1-git-send-email-chengang@emindsoft.com.cn> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 42.120.134.218 Cc: qemu-devel@nongnu.org, Chen Gang Subject: [Qemu-devel] [PATCH v5 1/5] fpu: softfloat: Add normalize_roundpack_float32 function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Chen Gang It is based on (u)int32_to_float32 function to support float32 packing. Signed-off-by: Chen Gang --- fpu/softfloat.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 8 +++++++ 2 files changed, 63 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index f1170fe..dba8566 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -7080,6 +7080,61 @@ float64 uint32_to_float64(uint32_t a, float_status *status) return int64_to_float64(a, status); } +/* + * The mantissa contents the hide bit, e.g. exp: 0x9e with sig: 1 means 1.0f. + * + * It references from int32_to_float32() and uint32_to_float32() + */ +float32 normalize_roundpack_float32(flag sign, int_fast16_t exp, uint32_t sig, + float_status *status) +{ + uint64_t absa = sig; + int8_t scount; + + if (exp >= 0xff) { + return packFloat32(sign, 0xFF, 0); + } else if (exp <= 0) { + shift32RightJamming(sig, 0 - exp, &sig); + return packFloat32(sign, 0, sig); + } + + if (sign) { + if (sig & 0x7FFFFFFF) { + return normalizeRoundAndPackFloat32(1, exp - 2, sig, status); + } + if (sig) { + return packFloat32(1, exp, 0); + } else { + return float32_zero; + } + } + + if (!sig) { + return float32_zero; + } + + scount = countLeadingZeros64(absa) - 40; + if (scount >= 0) { + exp -= 7 + scount + 2; + if (exp <= 0) { + return packFloat32(0, 0, absa); + } + return packFloat32(0, exp, absa << scount); + } + + scount += 7; + exp -= scount + 2; + if (exp <= 0) { + return packFloat32(0, 0, absa); + } + if (scount < 0) { + shift64RightJamming(absa, 0 - scount, &absa); + } else { + absa <<= scount; + } + return roundAndPackFloat32(0, exp, absa, status); +} + uint32 float32_to_uint32(float32 a, float_status *status) { int64_t v; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index ded34eb..4995a15 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -422,6 +422,14 @@ int float32_is_signaling_nan( float32 ); float32 float32_maybe_silence_nan( float32 ); float32 float32_scalbn(float32, int, float_status *status); +/* + * The mantissa contents the hide bit, e.g. exp: 0x9e with sig: 1 means 1.0f. + * + * It references from int32_to_float32() and uint32_to_float32() + */ +float32 normalize_roundpack_float32(flag sign, int_fast16_t exp, uint32_t sig, + float_status *status); + static inline float32 float32_abs(float32 a) { /* Note that abs does *not* handle NaN specially, nor does