From patchwork Wed Dec 23 21:48:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 560746 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 774F6140B94 for ; Thu, 24 Dec 2015 08:50:31 +1100 (AEDT) Received: from localhost ([::1]:58025 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aBrIj-0003gY-Ht for incoming@patchwork.ozlabs.org; Wed, 23 Dec 2015 16:50:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45878) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aBrIN-00035g-KB for qemu-devel@nongnu.org; Wed, 23 Dec 2015 16:50:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aBrIK-0004fQ-E2 for qemu-devel@nongnu.org; Wed, 23 Dec 2015 16:50:07 -0500 Received: from out11.biz.mail.alibaba.com ([205.204.114.131]:42144) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aBrIJ-0004d1-Ga for qemu-devel@nongnu.org; Wed, 23 Dec 2015 16:50:04 -0500 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.4009759|-1; FP=1478410998451161331|1|1|2|0|-1|-1|-1; HT=e01l07406; MF=chengang@emindsoft.com.cn; NM=1; PH=DS; RN=7; RT=6; SR=0; TI=SMTPD_----4Nunx7J_1450907393; Received: from localhost.localdomain.localdomain(mailfrom:chengang@emindsoft.com.cn ip:223.72.67.117) by smtp.aliyun-inc.com(10.147.40.44); Thu, 24 Dec 2015 05:49:53 +0800 From: chengang@emindsoft.com.cn To: rth@twiddle.net, peter.maydell@linaro.org, cmetcalf@ezchip.com Date: Thu, 24 Dec 2015 05:48:35 +0800 Message-Id: <1450907315-10135-5-git-send-email-chengang@emindsoft.com.cn> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1450907315-10135-1-git-send-email-chengang@emindsoft.com.cn> References: <1450907315-10135-1-git-send-email-chengang@emindsoft.com.cn> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 205.204.114.131 Cc: Chen Gang , qemu-devel@nongnu.org, Chen Gang Subject: [Qemu-devel] [PATCH v4 4/4] target-tilegx: Integrate floating pointer implementation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Chen Gang It passes normal building, and gcc testsuite. Signed-off-by: Chen Gang --- target-tilegx/Makefile.objs | 3 ++- target-tilegx/helper.h | 12 +++++++++ target-tilegx/translate.c | 66 ++++++++++++++++++++++++++++++++++++++------- 3 files changed, 71 insertions(+), 10 deletions(-) diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs index 0db778f..2f4ea92 100644 --- a/target-tilegx/Makefile.objs +++ b/target-tilegx/Makefile.objs @@ -1 +1,2 @@ -obj-y += cpu.o translate.o helper.o simd_helper.o +obj-y += cpu.o translate.o helper.o simd_helper.o \ + helper-fsingle.o helper-fdouble.o helper-fshared.o diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h index 9281d0f..3471fe3 100644 --- a/target-tilegx/helper.h +++ b/target-tilegx/helper.h @@ -24,3 +24,15 @@ DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) + +DEF_HELPER_2(fsingle_add1, i64, i64, i64) +DEF_HELPER_2(fsingle_sub1, i64, i64, i64) +DEF_HELPER_2(fsingle_mul1, i64, i64, i64) +DEF_HELPER_1(fsingle_pack2, i64, i64) +DEF_HELPER_2(fdouble_unpack_min, i64, i64, i64) +DEF_HELPER_2(fdouble_unpack_max, i64, i64, i64) +DEF_HELPER_2(fdouble_add_flags, i64, i64, i64) +DEF_HELPER_2(fdouble_sub_flags, i64, i64, i64) +DEF_HELPER_3(fdouble_addsub, i64, i64, i64, i64) +DEF_HELPER_2(fdouble_mul_flags, i64, i64, i64) +DEF_HELPER_3(fdouble_pack2, i64, i64, i64, i64) diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 354f25a..924eece 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -597,6 +597,11 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, } qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]); return ret; + + case OE_RR_X0(FSINGLE_PACK1): + case OE_RR_Y0(FSINGLE_PACK1): + mnemonic = "fsingle_pack1"; + goto done2; } tdest = dest_gr(dc, dest); @@ -613,9 +618,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, gen_helper_cnttz(tdest, tsrca); mnemonic = "cnttz"; break; - case OE_RR_X0(FSINGLE_PACK1): - case OE_RR_Y0(FSINGLE_PACK1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RR_X1(LD1S): memop = MO_SB; mnemonic = "ld1s"; /* prefetch_l1_fault */ @@ -734,6 +736,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, return TILEGX_EXCP_OPCODE_UNKNOWN; } +done2: qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic, reg_names[dest], reg_names[srca]); return ret; @@ -742,13 +745,21 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, unsigned dest, unsigned srca, unsigned srcb) { - TCGv tdest = dest_gr(dc, dest); - TCGv tsrca = load_gr(dc, srca); - TCGv tsrcb = load_gr(dc, srcb); + TCGv tdest, tsrca, tsrcb; TCGv t0; const char *mnemonic; switch (opext) { + case OE_RRR(FSINGLE_ADDSUB2, 0, X0): + mnemonic = "fsingle_addsub2"; + goto done2; + } + + tdest = dest_gr(dc, dest); + tsrca = load_gr(dc, srca); + tsrcb = load_gr(dc, srcb); + + switch (opext) { case OE_RRR(ADDXSC, 0, X0): case OE_RRR(ADDXSC, 0, X1): gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl); @@ -906,14 +917,37 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, mnemonic = "exch"; break; case OE_RRR(FDOUBLE_ADDSUB, 0, X0): + gen_helper_fdouble_addsub(tdest, load_gr(dc, dest), tsrca, tsrcb); + mnemonic = "fdouble_addsub"; + break; case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0): + gen_helper_fdouble_add_flags(tdest, tsrca, tsrcb); + mnemonic = "fdouble_add_flags"; + break; case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0): + gen_helper_fdouble_mul_flags(tdest, tsrca, tsrcb); + mnemonic = "fdouble_mul_flags"; + break; case OE_RRR(FDOUBLE_PACK1, 0, X0): + tcg_gen_mov_i64(tdest, tsrcb); + mnemonic = "fdouble_pack1"; + break; case OE_RRR(FDOUBLE_PACK2, 0, X0): + gen_helper_fdouble_pack2(tdest, load_gr(dc, dest), tsrca, tsrcb); + mnemonic = "fdouble_pack2"; + break; case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0): + gen_helper_fdouble_sub_flags(tdest, tsrca, tsrcb); + mnemonic = "fdouble_sub_flags"; + break; case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0): + gen_helper_fdouble_unpack_max(tdest, tsrca, tsrcb); + mnemonic = "fdouble_unpack_max"; + break; case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + gen_helper_fdouble_unpack_min(tdest, tsrca, tsrcb); + mnemonic = "fdouble_unpack_min"; + break; case OE_RRR(FETCHADD4, 0, X1): gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb, TILEGX_EXCP_OPCODE_FETCHADD4); @@ -955,12 +989,25 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, mnemonic = "fetchor"; break; case OE_RRR(FSINGLE_ADD1, 0, X0): - case OE_RRR(FSINGLE_ADDSUB2, 0, X0): + gen_helper_fsingle_add1(tdest, tsrca, tsrcb); + mnemonic = "fsingle_add1"; + break; case OE_RRR(FSINGLE_MUL1, 0, X0): + gen_helper_fsingle_mul1(tdest, tsrca, tsrcb); + mnemonic = "fsingle_mul1"; + break; case OE_RRR(FSINGLE_MUL2, 0, X0): + tcg_gen_mov_i64(tdest, tsrca); + mnemonic = "fsingle_mul2"; + break; case OE_RRR(FSINGLE_PACK2, 0, X0): + gen_helper_fsingle_pack2(tdest, tsrca); + mnemonic = "fsingle_pack2"; + break; case OE_RRR(FSINGLE_SUB1, 0, X0): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + gen_helper_fsingle_sub1(tdest, tsrca, tsrcb); + mnemonic = "fsingle_sub1"; + break; case OE_RRR(MNZ, 0, X0): case OE_RRR(MNZ, 0, X1): case OE_RRR(MNZ, 4, Y0): @@ -1464,6 +1511,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, return TILEGX_EXCP_OPCODE_UNKNOWN; } +done2: qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic, reg_names[dest], reg_names[srca], reg_names[srcb]); return TILEGX_EXCP_NONE;