From patchwork Mon Dec 14 08:41:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvise Rigo X-Patchwork-Id: 556333 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 20D711402BB for ; Mon, 14 Dec 2015 19:48:44 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=virtualopensystems-com.20150623.gappssmtp.com header.i=@virtualopensystems-com.20150623.gappssmtp.com header.b=Yki2rVpy; dkim-atps=neutral Received: from localhost ([::1]:58539 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8OoE-0000Db-2k for incoming@patchwork.ozlabs.org; Mon, 14 Dec 2015 03:48:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55624) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8Ohh-0005Z6-BE for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:42:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a8Ohf-0001uW-SC for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:41:57 -0500 Received: from mail-wm0-x230.google.com ([2a00:1450:400c:c09::230]:38286) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8Ohf-0001uJ-KX for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:41:55 -0500 Received: by wmpp66 with SMTP id p66so50472828wmp.1 for ; Mon, 14 Dec 2015 00:41:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=virtualopensystems-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FOD6KIxBseKlsch9qNPAli4abEf16YjmG7tntBIWJ2Q=; b=Yki2rVpyx+G8Is3R4x9yHQyZsct7EZyzjYDOGcrn2ooQjTi3HMYpqKfw+jMXml5anx 6ny/YU4apUrm84Iu5f3XkYCMds6DOjexOEGfZXJ7RQ96z3MiIGaJPhbAWdufVr98TPmb NkHGfMJXXRc1HeQtvL95tCWCwB8QdR0jU4qfe/g43r+Llq2XvzOfAiKj9M8oFKxioEQ6 3VdFrVfSVTP9ywK2A5rXDF7pEK4vLfLYKGrLnhgNumbiaZTLAFBN3ijCfLkJztxrg6e7 wvFTjY+NB3WxTBVqOSCGVuzI3jEY2FsHsMpMeb1tTSzzUiFf2BRgExlqVFIz8OMwttZq 0mDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FOD6KIxBseKlsch9qNPAli4abEf16YjmG7tntBIWJ2Q=; b=U7XyY2NAJsI7Idq27HlF2jjIlc9MEyS49hjWlJOSRHIVoYh58pEegqDzQLXK+1VOc8 UTOzIsc4nTwVGbDNFtP2DFOO6G5kkwj/koiyRepe03CqVPcNV5V/CCFXOSqmJJUHjw2K 6qdJ0+/xYAmB7k9VMPWDNnfMu7N8w9PTK+AhohQwn5FNGISUCJHrGgCeBF11eoWFwx+0 v6oLPm9p5TSRse7plZ8/F8bwwOj30KyiYIV2JX3oYnqh6g3eKoKbnwt/6KK5Il0/lQi5 nU1t0DSq/ZAHF77ISft3H9hsUlLfih9sum8WcokRsx8R4bkma5d80sGPO9244ZhJUq6I D1jg== X-Gm-Message-State: ALoCoQn6DQwxshjYS1MaUgNlgIwLY5n3Pgdf9PITLeAzIIE5qMKlvQRoeef68K1rM72JfI5cpGcQ6bgc2swB80x8gV56U/YRJg== X-Received: by 10.28.215.211 with SMTP id o202mr21511585wmg.85.1450082515031; Mon, 14 Dec 2015 00:41:55 -0800 (PST) Received: from localhost.localdomain (LPuteaux-656-1-278-113.w80-15.abo.wanadoo.fr. [80.15.154.113]) by smtp.googlemail.com with ESMTPSA id xs9sm1100526wjc.43.2015.12.14.00.41.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Dec 2015 00:41:54 -0800 (PST) From: Alvise Rigo To: qemu-devel@nongnu.org, mttcg@listserver.greensocs.com Date: Mon, 14 Dec 2015 09:41:31 +0100 Message-Id: <1450082498-27109-8-git-send-email-a.rigo@virtualopensystems.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> References: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::230 Cc: claudio.fontana@huawei.com, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, alex.bennee@linaro.org, rth@twiddle.net Subject: [Qemu-devel] [RFC v6 07/14] target-arm: translate: Use ld/st excl for atomic insns X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use the new LL/SC runtime helpers to handle the ARM atomic instructions in softmmu_llsc_template.h. In general, the helper generator gen_helper_{ldlink,stcond}_aa32_i{8,16,32,64}() calls the function helper_{le,be}_{ldlink,stcond}{ub,uw,ulq}_mmu() implemented in softmmu_llsc_template.h. Suggested-by: Jani Kokkonen Suggested-by: Claudio Fontana Signed-off-by: Alvise Rigo --- target-arm/translate.c | 101 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 97 insertions(+), 4 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 5d22879..e88d8a3 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -64,8 +64,10 @@ TCGv_ptr cpu_env; static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; static TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; +#ifndef CONFIG_TCG_USE_LDST_EXCL TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; +#endif #ifdef CONFIG_USER_ONLY TCGv_i64 cpu_exclusive_test; TCGv_i32 cpu_exclusive_info; @@ -98,10 +100,12 @@ void arm_translate_init(void) cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF"); cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF"); +#ifndef CONFIG_TCG_USE_LDST_EXCL cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUARMState, exclusive_addr), "exclusive_addr"); cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUARMState, exclusive_val), "exclusive_val"); +#endif #ifdef CONFIG_USER_ONLY cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUARMState, exclusive_test), "exclusive_test"); @@ -7414,15 +7418,59 @@ static void gen_logicq_cc(TCGv_i32 lo, TCGv_i32 hi) tcg_gen_or_i32(cpu_ZF, lo, hi); } -/* Load/Store exclusive instructions are implemented by remembering +/* If the softmmu is enabled, the translation of Load/Store exclusive + * instructions will rely on the gen_helper_{ldlink,stcond} helpers, + * offloading most of the work to the softmmu_llsc_template.h functions. + + Otherwise, these instructions are implemented by remembering the value/address loaded, and seeing if these are the same when the store is performed. This should be sufficient to implement the architecturally mandated semantics, and avoids having to monitor regular stores. - In system emulation mode only one CPU will be running at once, so - this sequence is effectively atomic. In user emulation mode we - throw an exception and handle the atomic operation elsewhere. */ + In user emulation mode we throw an exception and handle the atomic + operation elsewhere. */ +#ifdef CONFIG_TCG_USE_LDST_EXCL +static void gen_load_exclusive(DisasContext *s, int rt, int rt2, + TCGv_i32 addr, int size) + { + TCGv_i32 tmp = tcg_temp_new_i32(); + TCGv_i32 mem_idx = tcg_temp_new_i32(); + + tcg_gen_movi_i32(mem_idx, get_mem_index(s)); + + if (size != 3) { + switch (size) { + case 0: + gen_helper_ldlink_aa32_i8(tmp, cpu_env, addr, mem_idx); + break; + case 1: + gen_helper_ldlink_aa32_i16(tmp, cpu_env, addr, mem_idx); + break; + case 2: + gen_helper_ldlink_aa32_i32(tmp, cpu_env, addr, mem_idx); + break; + default: + abort(); + } + + store_reg(s, rt, tmp); + } else { + TCGv_i64 tmp64 = tcg_temp_new_i64(); + TCGv_i32 tmph = tcg_temp_new_i32(); + + gen_helper_ldlink_aa32_i64(tmp64, cpu_env, addr, mem_idx); + tcg_gen_extr_i64_i32(tmp, tmph, tmp64); + + store_reg(s, rt, tmp); + store_reg(s, rt2, tmph); + + tcg_temp_free_i64(tmp64); + } + + tcg_temp_free_i32(mem_idx); +} +#else static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i32 addr, int size) { @@ -7461,10 +7509,14 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, store_reg(s, rt, tmp); tcg_gen_extu_i32_i64(cpu_exclusive_addr, addr); } +#endif static void gen_clrex(DisasContext *s) { +#ifdef CONFIG_TCG_USE_LDST_EXCL +#else tcg_gen_movi_i64(cpu_exclusive_addr, -1); +#endif } #ifdef CONFIG_USER_ONLY @@ -7476,6 +7528,47 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, size | (rd << 4) | (rt << 8) | (rt2 << 12)); gen_exception_internal_insn(s, 4, EXCP_STREX); } +#elif defined CONFIG_TCG_USE_LDST_EXCL +static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, + TCGv_i32 addr, int size) +{ + TCGv_i32 tmp, mem_idx; + + mem_idx = tcg_temp_new_i32(); + + tcg_gen_movi_i32(mem_idx, get_mem_index(s)); + tmp = load_reg(s, rt); + + if (size != 3) { + switch (size) { + case 0: + gen_helper_stcond_aa32_i8(cpu_R[rd], cpu_env, addr, tmp, mem_idx); + break; + case 1: + gen_helper_stcond_aa32_i16(cpu_R[rd], cpu_env, addr, tmp, mem_idx); + break; + case 2: + gen_helper_stcond_aa32_i32(cpu_R[rd], cpu_env, addr, tmp, mem_idx); + break; + default: + abort(); + } + } else { + TCGv_i64 tmp64; + TCGv_i32 tmp2; + + tmp64 = tcg_temp_new_i64(); + tmp2 = load_reg(s, rt2); + tcg_gen_concat_i32_i64(tmp64, tmp, tmp2); + gen_helper_stcond_aa32_i64(cpu_R[rd], cpu_env, addr, tmp64, mem_idx); + + tcg_temp_free_i32(tmp2); + tcg_temp_free_i64(tmp64); + } + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(mem_idx); +} #else static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, TCGv_i32 addr, int size)