| Message ID | 1445608598-24485-2-git-send-email-mark.cave-ayland@ilande.co.uk |
|---|---|
| State | New |
| Headers | show |
On 23/10/15 15:56, Mark Cave-Ayland wrote: > From: Alexander Graf <agraf@suse.de> > > According to the ISA setting the Rc bit on mtspr is undefined behavior. > Real 750 hardware simply ignores the bit and doesn't touch cr0 though. According to PowerISA 2.07, chapter 1.1.3: "Reserved fields in instructions are ignored by the pro- cessor." And the lowest bit of the mtspr opcode is marked as reserved. So I think this is not just a hack, but even a proper fix. > Unfortunately, Mac OS 9 relies on this fact and executes a few mtspr > instructions (to set XER for example) with Rc set. > > So let's handle the bit the same way hardware does and ignore it. > > Signed-off-by: Alexander Graf <agraf@suse.de> > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > --- > target-ppc/translate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index c2bc1a7..d1f0f13 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -9884,7 +9884,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), > GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), > #endif > GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), > -GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), > +GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), > GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), > GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), > GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), Reviewed-by: Thomas Huth <thuth@redhat.com>
On Fri, Oct 23, 2015 at 02:56:26PM +0100, Mark Cave-Ayland wrote: > From: Alexander Graf <agraf@suse.de> > > According to the ISA setting the Rc bit on mtspr is undefined behavior. > Real 750 hardware simply ignores the bit and doesn't touch cr0 though. > > Unfortunately, Mac OS 9 relies on this fact and executes a few mtspr > instructions (to set XER for example) with Rc set. > > So let's handle the bit the same way hardware does and ignore it. > > Signed-off-by: Alexander Graf <agraf@suse.de> > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > target-ppc/translate.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index c2bc1a7..d1f0f13 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -9884,7 +9884,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), > GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), > #endif > GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), > -GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), > +GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), > GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), > GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), > GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index c2bc1a7..d1f0f13 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9884,7 +9884,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), #endif GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), -GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), +GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),