From patchwork Thu Oct 1 11:01:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 525088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 179A0140D6E for ; Fri, 2 Oct 2015 01:00:09 +1000 (AEST) Received: from localhost ([::1]:51423 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhfL4-0004sy-TI for incoming@patchwork.ozlabs.org; Thu, 01 Oct 2015 11:00:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zhbcg-0001rE-Pl for qemu-devel@nongnu.org; Thu, 01 Oct 2015 07:02:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zhbcd-00072q-Ka for qemu-devel@nongnu.org; Thu, 01 Oct 2015 07:02:02 -0400 Received: from smtpbg298.qq.com ([184.105.67.102]:60836) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zhbcd-00070C-DU for qemu-devel@nongnu.org; Thu, 01 Oct 2015 07:01:59 -0400 X-QQ-mid: esmtp37t1443697290t156t02600 Received: from localhost.localdomain.localdoma (unknown [223.72.67.87]) by esmtp5.qq.com (ESMTP) with id ; Thu, 01 Oct 2015 19:01:28 +0800 (CST) X-QQ-SSF: 01000000000000F0FH700F00002000H X-QQ-FEAT: sQM3mSWMFDy4sc860TuApsyIdzIODhp/+6jc4qCnR9SsDa9tlJg1RwJHiupX/ S7hpfazbZ980xjHt2dwrA9TgXIJWMnGwnI0LvSJJcYcNkjH6xjvtTNb0RFNcd7ny/oD1IxL 9Gb6HHsplgIpAZ52YduUxjajI1YZigeyOj6pjQ56ro+3LtvJn67gJ1/hjJbNXixgST1svy1 pdEIVE/Sh30JQamDGBjMtd0O3diiu5jtxuA/73E7ybP/IYYpZxJDt X-QQ-GoodBg: 0 X-QQ-CSender: gang.chen.5i5j@qq.com From: gang.chen.5i5j@gmail.com To: peter.maydell@linaro.org, rth@twiddle.net Date: Thu, 1 Oct 2015 19:01:26 +0800 Message-Id: <1443697286-2641-1-git-send-email-gang.chen.5i5j@gmail.com> X-Mailer: git-send-email 1.9.3 X-QQ-SENDSIZE: 520 X-QQ-FName: 0935036A914B4325A3C00FCED72EA417 X-QQ-LocalIP: 163.177.66.155 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 184.105.67.102 Cc: cmetcalf@ezchip.com, qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com, Chen Gang Subject: [Qemu-devel] [PATCH v2] target-tilegx: Support iret instruction and related special registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Chen Gang Acording to the __longjmp tilegx libc implementation, and reference from tilegx ISA document, we can left iret instruction empty. The related code is below: ENTRY (__longjmp) FEEDBACK_ENTER(__longjmp) #define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE } FOR_EACH_CALLEE_SAVED_REG(RESTORE) { LD r2, r0 ; retrieve ICS bit from jmp_buf movei r3, 1 CMPEQI r0, r1, 0 } { mtspr INTERRUPT_CRITICAL_SECTION, r3 shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT } { mtspr EX_CONTEXT_0_0, lr ori r2, r2, RETURN_PL } { or r0, r1, r0 mtspr EX_CONTEXT_0_1, r2 } iret jrp lr Until now, EX_CONTEXT_0_0 and EX_CONTEXT_0_1 are only used in mtspr, so just skip them, at present. After this patch, busybox sh can run correctly. Signed-off-by: Chen Gang --- target-tilegx/translate.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 421766b..3ae59fe 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -563,8 +563,10 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, break; case OE_RR_X0(FSINGLE_PACK1): case OE_RR_Y0(FSINGLE_PACK1): - case OE_RR_X1(IRET): return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + case OE_RR_X1(IRET): + mnemonic = "iret"; + break; case OE_RR_X1(LD1S): memop = MO_SB; mnemonic = "ld1s"; /* prefetch_l1_fault */ @@ -1823,6 +1825,8 @@ static const TileSPR *find_spr(unsigned spr) offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0) D(SIM_CONTROL, offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0) + D(EX_CONTEXT_0_0, -1, 0, 0) /* Skip it */ + D(EX_CONTEXT_0_1, -1, 0, 0) /* Skip it */ } #undef D @@ -1836,9 +1840,11 @@ static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca) const TileSPR *def = find_spr(spr); TCGv tsrca; - if (def == NULL) { + if (!def) { qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr, reg_names[srca]); return TILEGX_EXCP_OPCODE_UNKNOWN; + } else if (def->offset == -1) { + goto tail; } tsrca = load_gr(dc, srca); @@ -1847,6 +1853,8 @@ static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca) } else { tcg_gen_st_tl(tsrca, cpu_env, def->offset); } + +tail: qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, %s", def->name, reg_names[srca]); return TILEGX_EXCP_NONE; } @@ -1856,7 +1864,7 @@ static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned dest, unsigned spr) const TileSPR *def = find_spr(spr); TCGv tdest; - if (def == NULL) { + if (!def || def->offset == -1) { qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest], spr); return TILEGX_EXCP_OPCODE_UNKNOWN; }