@@ -563,8 +563,10 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
break;
case OE_RR_X0(FSINGLE_PACK1):
case OE_RR_Y0(FSINGLE_PACK1):
- case OE_RR_X1(IRET):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ case OE_RR_X1(IRET):
+ mnemonic = "iret";
+ break;
case OE_RR_X1(LD1S):
memop = MO_SB;
mnemonic = "ld1s"; /* prefetch_l1_fault */
@@ -1823,6 +1825,8 @@ static const TileSPR *find_spr(unsigned spr)
offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
D(SIM_CONTROL,
offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
+ D(EX_CONTEXT_0_0, -1, 0, 0) /* Skip it */
+ D(EX_CONTEXT_0_1, -1, 0, 0) /* Skip it */
}
#undef D
@@ -1836,9 +1840,11 @@ static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca)
const TileSPR *def = find_spr(spr);
TCGv tsrca;
- if (def == NULL) {
+ if (!def) {
qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr, reg_names[srca]);
return TILEGX_EXCP_OPCODE_UNKNOWN;
+ } else if (def->offset == -1) {
+ goto tail;
}
tsrca = load_gr(dc, srca);
@@ -1847,6 +1853,8 @@ static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca)
} else {
tcg_gen_st_tl(tsrca, cpu_env, def->offset);
}
+
+tail:
qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, %s", def->name, reg_names[srca]);
return TILEGX_EXCP_NONE;
}
@@ -1856,7 +1864,7 @@ static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned dest, unsigned spr)
const TileSPR *def = find_spr(spr);
TCGv tdest;
- if (def == NULL) {
+ if (!def || def->offset == -1) {
qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest], spr);
return TILEGX_EXCP_OPCODE_UNKNOWN;
}