From patchwork Mon Sep 28 22:06:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 523695 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 26D3014029C for ; Tue, 29 Sep 2015 13:04:42 +1000 (AEST) Received: from localhost ([::1]:44305 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZglDc-0008MQ-1z for incoming@patchwork.ozlabs.org; Mon, 28 Sep 2015 23:04:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37652) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZggZe-0005YG-Vv for qemu-devel@nongnu.org; Mon, 28 Sep 2015 18:07:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZggZb-0002nw-J5 for qemu-devel@nongnu.org; Mon, 28 Sep 2015 18:07:06 -0400 Received: from smtpbg62.qq.com ([103.7.29.139]:31414 helo=smtpbg64.qq.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZggZb-0002nP-0M for qemu-devel@nongnu.org; Mon, 28 Sep 2015 18:07:03 -0400 X-QQ-mid: esmtp36t1443478012t847t31169 Received: from localhost.localdomain (unknown [223.72.67.27]) by esmtp5.qq.com (ESMTP) with id ; Tue, 29 Sep 2015 06:06:51 +0800 (CST) X-QQ-SSF: 01000000000000F0FH700F00002000H X-QQ-FEAT: jVc9qW+oM4scBEMqiihQRwkJTp6WPbmyjqTNVyIWkjk/quvmhJimCC3Dq/XKy jAcNm3PHo0hUCfzqWvARvzU/udphXSeYTSeIkqJL4Ofb8CjbpZnP1Hl6JKnqc7HI319/5Ae C7+BMOqcCCJZDMyRyAJbOtuXV65Y2LsgcfOrFwWBIHTG+LjzjnFNYdTt/V2fzOKUXjauPaW DZFPMxyYPi/cbkDhOcLap7M9/jD+S28ulseoHzHHVXJg39UtOAWoM X-QQ-GoodBg: 0 X-QQ-CSender: gang.chen.5i5j@qq.com From: gang.chen.5i5j@gmail.com To: peter.maydell@linaro.org, rth@twiddle.net Date: Tue, 29 Sep 2015 06:06:50 +0800 Message-Id: <1443478010-2620-1-git-send-email-gang.chen.5i5j@gmail.com> X-Mailer: git-send-email 1.9.3 X-QQ-SENDSIZE: 520 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 103.7.29.139 Cc: cmetcalf@ezchip.com, qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com, Chen Gang Subject: [Qemu-devel] [PATCH] target-tilegx: Support iret instruction and related special registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Chen Gang Acording to the __longjmp tilegx libc implementation, and reference from tilegx ISA document, we can left iret instruction empty. The related code is below: ENTRY (__longjmp) FEEDBACK_ENTER(__longjmp) #define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE } FOR_EACH_CALLEE_SAVED_REG(RESTORE) { LD r2, r0 ; retrieve ICS bit from jmp_buf movei r3, 1 CMPEQI r0, r1, 0 } { mtspr INTERRUPT_CRITICAL_SECTION, r3 shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT } { mtspr EX_CONTEXT_0_0, lr ori r2, r2, RETURN_PL } { or r0, r1, r0 mtspr EX_CONTEXT_0_1, r2 } iret jrp lr So can let busybox sh run correctly. Signed-off-by: Chen Gang --- target-tilegx/cpu.h | 2 ++ target-tilegx/translate.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h index 4b05cd2..02e1a18 100644 --- a/target-tilegx/cpu.h +++ b/target-tilegx/cpu.h @@ -54,6 +54,8 @@ enum { TILEGX_SPR_CRITICAL_SEC = 1, TILEGX_SPR_SIM_CONTROL = 2, TILEGX_SPR_EX_CONTEXT_1 = 3, + TILEGX_SPR_EX_CONTEXT_0_0 = 4, + TILEGX_SPR_EX_CONTEXT_0_1 = 5, TILEGX_SPR_COUNT }; diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 7232361..77447ec 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -562,8 +562,10 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, break; case OE_RR_X0(FSINGLE_PACK1): case OE_RR_Y0(FSINGLE_PACK1): - case OE_RR_X1(IRET): return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + case OE_RR_X1(IRET): + mnemonic = "iret"; + break; case OE_RR_X1(LD1S): memop = MO_SB; mnemonic = "ld1s"; @@ -1813,6 +1815,10 @@ static const TileSPR *find_spr(unsigned spr) offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0) D(SIM_CONTROL, offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0) + D(EX_CONTEXT_0_0, + offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_0]), 0, 0) + D(EX_CONTEXT_0_1, + offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_1]), 0, 0) } #undef D