From patchwork Thu Sep 24 08:32:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvise Rigo X-Patchwork-Id: 522164 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 335C41401F6 for ; Thu, 24 Sep 2015 18:30:05 +1000 (AEST) Received: from localhost ([::1]:53665 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zf1uk-0005zr-TA for incoming@patchwork.ozlabs.org; Thu, 24 Sep 2015 04:30:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52069) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zf1u2-0004qH-30 for qemu-devel@nongnu.org; Thu, 24 Sep 2015 04:29:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zf1tx-0007X3-Up for qemu-devel@nongnu.org; Thu, 24 Sep 2015 04:29:17 -0400 Received: from mail-wi0-f176.google.com ([209.85.212.176]:34299) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zf1tx-0007Wr-MQ for qemu-devel@nongnu.org; Thu, 24 Sep 2015 04:29:13 -0400 Received: by wicfx3 with SMTP id fx3so17372563wic.1 for ; Thu, 24 Sep 2015 01:29:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IQPlATjufvTToCcEQmrhlsU75TgsdDDB8XxCro8ZBy0=; b=fEJUr5cYMDNKbPdJUCi/ocCj9xSrN3aP1SgL+c9uoVD8MKeb+URQ93xGrVcHdGH1O+ 4yuga6b0H9WzdnxKGnYgZHjdLomDFMrQf6Z7X4OB4xABpsU9cqIZg59lUOz1uYPLQTEo JYAYmG6Uuu48VaeRiP0p78Ki8IEb6f7IOVe3nwFhjk/12nKIW+ooLEFmkLY5z/7W54yA E67L7ou0bq9YUQWSCmIL4JyuYfWnNhmzU6cC/WkccKLlNwC/mH7ZWFlMfH003aMp6E9E ZDqpUyYgfFJ4ZV1+kQcW4mJ23JvhvlFHgznWP8j3joJ9VPjLC3PhyoCObgB/6NAia0jw ZjXg== X-Gm-Message-State: ALoCoQk+72q/JKCJAS5gx3Db+2lMr34lGWuOWBRQiLhMsQWKWsmCQDRsMTUiABJBaf2aYVTj5Kxx X-Received: by 10.194.60.115 with SMTP id g19mr39131204wjr.29.1443083353192; Thu, 24 Sep 2015 01:29:13 -0700 (PDT) Received: from linarch.home (LPuteaux-656-1-278-113.w80-15.abo.wanadoo.fr. [80.15.154.113]) by smtp.googlemail.com with ESMTPSA id iw8sm5495668wjb.5.2015.09.24.01.29.12 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Sep 2015 01:29:12 -0700 (PDT) From: Alvise Rigo To: qemu-devel@nongnu.org, mttcg@listserver.greensocs.com Date: Thu, 24 Sep 2015 10:32:44 +0200 Message-Id: <1443083566-10994-5-git-send-email-a.rigo@virtualopensystems.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: <1443083566-10994-1-git-send-email-a.rigo@virtualopensystems.com> References: <1443083566-10994-1-git-send-email-a.rigo@virtualopensystems.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.212.176 Cc: alex.bennee@linaro.org, jani.kokkonen@huawei.com, tech@virtualopensystems.com, claudio.fontana@huawei.com, pbonzini@redhat.com Subject: [Qemu-devel] [RFC v5 4/6] target-arm: Create new runtime helpers for excl accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduce a set of new runtime helpers do handle exclusive instructions. This helpers are used as hooks to call the respective LL/SC helpers in softmmu_llsc_template.h from TCG code. Suggested-by: Jani Kokkonen Suggested-by: Claudio Fontana Signed-off-by: Alvise Rigo --- target-arm/helper.h | 10 ++++++ target-arm/op_helper.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/target-arm/helper.h b/target-arm/helper.h index 827b33d..8e7a7c2 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -530,6 +530,16 @@ DEF_HELPER_2(dc_zva, void, env, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_3(ldlink_aa32_i8, i32, env, i32, i32) +DEF_HELPER_3(ldlink_aa32_i16, i32, env, i32, i32) +DEF_HELPER_3(ldlink_aa32_i32, i32, env, i32, i32) +DEF_HELPER_3(ldlink_aa32_i64, i64, env, i32, i32) + +DEF_HELPER_4(stcond_aa32_i8, i32, env, i32, i32, i32) +DEF_HELPER_4(stcond_aa32_i16, i32, env, i32, i32, i32) +DEF_HELPER_4(stcond_aa32_i32, i32, env, i32, i32, i32) +DEF_HELPER_4(stcond_aa32_i64, i32, env, i32, i64, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 663c05d..d832ba8 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -969,3 +969,97 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i) return ((uint32_t)x >> shift) | (x << (32 - shift)); } } + +/* LoadLink helpers, only unsigned. */ +static void * const qemu_ldex_helpers[16] = { + [MO_UB] = helper_ret_ldlinkub_mmu, + + [MO_LEUW] = helper_le_ldlinkuw_mmu, + [MO_LEUL] = helper_le_ldlinkul_mmu, + [MO_LEQ] = helper_le_ldlinkq_mmu, + + [MO_BEUW] = helper_be_ldlinkuw_mmu, + [MO_BEUL] = helper_be_ldlinkul_mmu, + [MO_BEQ] = helper_be_ldlinkq_mmu, +}; + +#define LDEX_HELPER(SUFF, OPC) \ +uint32_t HELPER(ldlink_aa32_i##SUFF)(CPUARMState *env, uint32_t addr, \ + uint32_t index) \ +{ \ + CPUArchState *state = env; \ + TCGMemOpIdx op; \ + \ + op = make_memop_idx(OPC, index); \ + \ + tcg_target_ulong (*func)(CPUArchState *env, target_ulong addr, \ + TCGMemOpIdx oi, uintptr_t retaddr); \ + func = qemu_ldex_helpers[OPC]; \ + \ + return (uint32_t)func(state, addr, op, GETRA()); \ +} + +LDEX_HELPER(8, MO_UB) +LDEX_HELPER(16, MO_TEUW) +LDEX_HELPER(32, MO_TEUL) + +uint64_t HELPER(ldlink_aa32_i64)(CPUARMState *env, uint32_t addr, + uint32_t index) +{ + CPUArchState *state = env; + TCGMemOpIdx op; + + op = make_memop_idx(MO_TEQ, index); + + uint64_t (*func)(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr); + func = qemu_ldex_helpers[MO_TEQ]; + + return func(state, addr, op, GETRA()); +} + +/* StoreConditional helpers. Use the macro below to access them. */ +static void * const qemu_stex_helpers[16] = { + [MO_UB] = helper_ret_stcondb_mmu, + [MO_LEUW] = helper_le_stcondw_mmu, + [MO_LEUL] = helper_le_stcondl_mmu, + [MO_LEQ] = helper_le_stcondq_mmu, + [MO_BEUW] = helper_be_stcondw_mmu, + [MO_BEUL] = helper_be_stcondl_mmu, + [MO_BEQ] = helper_be_stcondq_mmu, +}; + +#define STEX_HELPER(SUFF, DATA_TYPE, OPC) \ +uint32_t HELPER(stcond_aa32_i##SUFF)(CPUARMState *env, uint32_t addr, \ + uint32_t val, uint32_t index) \ +{ \ + CPUArchState *state = env; \ + TCGMemOpIdx op; \ + \ + op = make_memop_idx(OPC, index); \ + \ + tcg_target_ulong (*func)(CPUArchState *env, target_ulong addr, \ + DATA_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr); \ + func = qemu_stex_helpers[OPC]; \ + \ + return (uint32_t)func(state, addr, val, op, GETRA()); \ +} + +STEX_HELPER(8, uint8_t, MO_UB) +STEX_HELPER(16, uint16_t, MO_TEUW) +STEX_HELPER(32, uint32_t, MO_TEUL) + +uint32_t HELPER(stcond_aa32_i64)(CPUARMState *env, uint32_t addr, + uint64_t val, uint32_t index) +{ + CPUArchState *state = env; + TCGMemOpIdx op; + + op = make_memop_idx(MO_TEQ, index); + + tcg_target_ulong (*func)(CPUArchState *env, target_ulong addr, + uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr); + func = qemu_stex_helpers[MO_TEQ]; + + return (uint32_t)func(state, addr, val, op, GETRA()); +}