From patchwork Tue Sep 22 13:18:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Denis V. Lunev" X-Patchwork-Id: 521040 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5D18D1401CD for ; Tue, 22 Sep 2015 23:21:29 +1000 (AEST) Received: from localhost ([::1]:39562 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZeNVf-0007cn-FS for incoming@patchwork.ozlabs.org; Tue, 22 Sep 2015 09:21:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58273) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZeNSv-0003Eq-6x for qemu-devel@nongnu.org; Tue, 22 Sep 2015 09:18:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZeNSs-0001dg-3G for qemu-devel@nongnu.org; Tue, 22 Sep 2015 09:18:37 -0400 Received: from mailhub.sw.ru ([195.214.232.25]:19999 helo=relay.sw.ru) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZeNSr-0001ZD-NB for qemu-devel@nongnu.org; Tue, 22 Sep 2015 09:18:33 -0400 Received: from irbis.sw.ru ([10.24.38.119]) by relay.sw.ru (8.13.4/8.13.4) with ESMTP id t8MDILXG006018; Tue, 22 Sep 2015 16:18:25 +0300 (MSK) From: "Denis V. Lunev" To: Date: Tue, 22 Sep 2015 16:18:13 +0300 Message-Id: <1442927901-1084-2-git-send-email-den@openvz.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1442927901-1084-1-git-send-email-den@openvz.org> References: <1442927901-1084-1-git-send-email-den@openvz.org> MIME-Version: 1.0 X-MIME-Autoconverted: from 8bit to quoted-printable by relay.sw.ru id t8MDILXG006018 X-detected-operating-system: by eggs.gnu.org: OpenBSD 3.x X-Received-From: 195.214.232.25 Cc: "Denis V. Lunev" , Paolo Bonzini , qemu-devel@nongnu.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Pavel Butsykin Subject: [Qemu-devel] [PATCH 1/9] apic_internal.h: make some apic_get_* functions externally visible X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Pavel Butsykin Move apic_get_bit(), apic_set_bit() to apic_internal.h, make the apic_get_ppr symbol external. It's necessary to work with isr, tmr, irr and ppr outside hw/intc/apic.c Signed-off-by: Pavel Butsykin Signed-off-by: Denis V. Lunev CC: Paolo Bonzini CC: Andreas Färber --- hw/intc/apic.c | 18 +----------------- include/hw/i386/apic_internal.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 77b639c..52ac8b2 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -51,14 +51,6 @@ static int apic_ffs_bit(uint32_t value) return ctz32(value); } -static inline void apic_set_bit(uint32_t *tab, int index) -{ - int i, mask; - i = index >> 5; - mask = 1 << (index & 0x1f); - tab[i] |= mask; -} - static inline void apic_reset_bit(uint32_t *tab, int index) { int i, mask; @@ -67,14 +59,6 @@ static inline void apic_reset_bit(uint32_t *tab, int index) tab[i] &= ~mask; } -static inline int apic_get_bit(uint32_t *tab, int index) -{ - int i, mask; - i = index >> 5; - mask = 1 << (index & 0x1f); - return !!(tab[i] & mask); -} - /* return -1 if no bit is set */ static int get_highest_priority_int(uint32_t *tab) { @@ -318,7 +302,7 @@ static uint8_t apic_get_tpr(APICCommonState *s) return s->tpr >> 4; } -static int apic_get_ppr(APICCommonState *s) +int apic_get_ppr(APICCommonState *s) { int tpr, isrv, ppr; diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h index 26632ac..5a213bc 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -147,4 +147,22 @@ void apic_enable_vapic(DeviceState *d, hwaddr paddr); void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip, TPRAccess access); +int apic_get_ppr(APICCommonState *s); + +static inline void apic_set_bit(uint32_t *tab, int index) +{ + int i, mask; + i = index >> 5; + mask = 1 << (index & 0x1f); + tab[i] |= mask; +} + +static inline int apic_get_bit(uint32_t *tab, int index) +{ + int i, mask; + i = index >> 5; + mask = 1 << (index & 0x1f); + return !!(tab[i] & mask); +} + #endif /* !QEMU_APIC_INTERNAL_H */