From patchwork Mon Sep 21 21:47:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 520592 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 21DC814018C for ; Tue, 22 Sep 2015 07:48:28 +1000 (AEST) Received: from localhost ([::1]:34131 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ze8wk-0005oc-1o for incoming@patchwork.ozlabs.org; Mon, 21 Sep 2015 17:48:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58277) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ze8wJ-0005Mq-1l for qemu-devel@nongnu.org; Mon, 21 Sep 2015 17:48:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ze8wF-0004tB-SJ for qemu-devel@nongnu.org; Mon, 21 Sep 2015 17:47:58 -0400 Received: from smtpbg298.qq.com ([184.105.67.102]:47330) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ze8wF-0004rJ-HB for qemu-devel@nongnu.org; Mon, 21 Sep 2015 17:47:55 -0400 X-QQ-mid: esmtp23t1442872058t027t31900 Received: from localhost.localdomain (unknown [223.72.67.123]) by esmtp4.qq.com (ESMTP) with id ; Tue, 22 Sep 2015 05:47:36 +0800 (CST) X-QQ-SSF: 01000000000000F0FG500F00002000H X-QQ-FEAT: Ydli/3lJ1ZouJF3nsE0zlYLjF0wBa47os/Bq0zy9oo5XAFgNAtl+uXDfbb5XH ayznPdUmMieL1miqKO0Ys4WgTy+L2Yy87e+ZLXMvDCJQK+hl0EJJ4+kCIsePQb71TxP3Zs3 8KspGZOiH2VSIoVZFjLhEGP1a4MEtGgIcHCfTPSgOb3Ac4EyrBghhtTj30r7CBpIRzG5Kwt RoZoOFpxABieFj6AiwISwctc3R4h5SRZrVYBjLP58ESwvByY+pzJM X-QQ-GoodBg: 0 X-QQ-CSender: gang.chen.5i5j@qq.com From: gang.chen.5i5j@gmail.com To: peter.maydell@linaro.org, rth@twiddle.net Date: Tue, 22 Sep 2015 05:47:35 +0800 Message-Id: <1442872055-2836-1-git-send-email-gang.chen.5i5j@gmail.com> X-Mailer: git-send-email 1.9.3 X-QQ-SENDSIZE: 520 X-QQ-FName: 860F9F94308C4224890A087CBE562060 X-QQ-LocalIP: 163.177.66.155 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 184.105.67.102 Cc: qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com, Chen Gang Subject: [Qemu-devel] [PATCH v2] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Chen Gang v2sh* are implemented with helper fucntions, according to the v1sh* implementations. v4sh* are implmeneted in normal code. Signed-off-by: Chen Gang --- target-tilegx/helper.h | 3 +++ target-tilegx/simd_helper.c | 31 +++++++++++++++++++++++++++++++ target-tilegx/translate.c | 39 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h index 766f5f2..b253722 100644 --- a/target-tilegx/helper.h +++ b/target-tilegx/helper.h @@ -8,3 +8,6 @@ DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c index b931929..c03e31a 100644 --- a/target-tilegx/simd_helper.c +++ b/target-tilegx/simd_helper.c @@ -32,6 +32,15 @@ uint64_t helper_v1shl(uint64_t a, uint64_t b) return (a & m) << b; } +uint64_t helper_v2shl(uint64_t a, uint64_t b) +{ + uint64_t m; + + b &= 15; + m = 0x0001000100010001ULL * (0xffff >> b); + return (a & m) << b; +} + uint64_t helper_v1shru(uint64_t a, uint64_t b) { uint64_t m; @@ -41,6 +50,15 @@ uint64_t helper_v1shru(uint64_t a, uint64_t b) return (a & m) >> b; } +uint64_t helper_v2shru(uint64_t a, uint64_t b) +{ + uint64_t m; + + b &= 15; + m = 0x0001000100010001ULL * ((0xffff << b) & 0xffff); + return (a & m) >> b; +} + uint64_t helper_v1shrs(uint64_t a, uint64_t b) { uint64_t r = 0; @@ -53,3 +71,16 @@ uint64_t helper_v1shrs(uint64_t a, uint64_t b) } return r; } + +uint64_t helper_v2shrs(uint64_t a, uint64_t b) +{ + uint64_t r = 0; + int i; + + b &= 15; + for (i = 0; i < 64; i += 16) { + int64_t ae = (int16_t)(a >> i); + r |= ((ae >> b) & 0xffff) << i; + } + return r; +} diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index e70c3e5..9228751 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -339,6 +339,25 @@ static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb return TILEGX_EXCP_NONE; } +static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64, + void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 al = tcg_temp_new_i32(); + TCGv_i32 ah = tcg_temp_new_i32(); + TCGv_i32 bl = tcg_temp_new_i32(); + + tcg_gen_extr_i64_i32(al, ah, a64); + tcg_gen_extrl_i64_i32(bl, b64); + tcg_gen_andi_i32(bl, bl, 31); + generate(al, al, bl); + generate(ah, ah, bl); + tcg_gen_concat_i32_i64(d64, al, ah); + + tcg_temp_free_i32(al); + tcg_temp_free_i32(ah); + tcg_temp_free_i32(bl); +} + static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, unsigned dest, unsigned srca) { @@ -1144,12 +1163,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(V2SADU, 0, X0): case OE_RRR(V2SHLSC, 0, X0): case OE_RRR(V2SHLSC, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V2SHL, 0, X0): case OE_RRR(V2SHL, 0, X1): + gen_helper_v2shl(tdest, tsrca, tsrcb); + mnemonic = "v2shl"; + break; case OE_RRR(V2SHRS, 0, X0): case OE_RRR(V2SHRS, 0, X1): + gen_helper_v2shrs(tdest, tsrca, tsrcb); + mnemonic = "v2shrs"; + break; case OE_RRR(V2SHRU, 0, X0): case OE_RRR(V2SHRU, 0, X1): + gen_helper_v2shru(tdest, tsrca, tsrcb); + mnemonic = "v2shru"; + break; case OE_RRR(V2SUBSC, 0, X0): case OE_RRR(V2SUBSC, 0, X1): case OE_RRR(V2SUB, 0, X0): @@ -1174,12 +1203,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(V4PACKSC, 0, X1): case OE_RRR(V4SHLSC, 0, X0): case OE_RRR(V4SHLSC, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V4SHL, 0, X0): case OE_RRR(V4SHL, 0, X1): + gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shl_i32); + mnemonic = "v4shl"; + break; case OE_RRR(V4SHRS, 0, X0): case OE_RRR(V4SHRS, 0, X1): + gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_sar_i32); + mnemonic = "v4shrs"; + break; case OE_RRR(V4SHRU, 0, X0): case OE_RRR(V4SHRU, 0, X1): + gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shr_i32); + mnemonic = "v4shru"; + break; case OE_RRR(V4SUBSC, 0, X0): case OE_RRR(V4SUBSC, 0, X1): case OE_RRR(V4SUB, 0, X0):