From patchwork Fri Sep 18 23:41:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Gang X-Patchwork-Id: 519609 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2D19D140785 for ; Sat, 19 Sep 2015 09:42:44 +1000 (AEST) Received: from localhost ([::1]:42514 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zd5Ig-0006E2-5s for incoming@patchwork.ozlabs.org; Fri, 18 Sep 2015 19:42:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zd5IF-0005lx-59 for qemu-devel@nongnu.org; Fri, 18 Sep 2015 19:42:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zd5IB-0000x2-4O for qemu-devel@nongnu.org; Fri, 18 Sep 2015 19:42:15 -0400 Received: from smtpbg299.qq.com ([184.105.67.99]:52299) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zd5IA-0000q8-M1 for qemu-devel@nongnu.org; Fri, 18 Sep 2015 19:42:10 -0400 X-QQ-mid: esmtp31t1442619716t733t18505 Received: from localhost.localdomain (unknown [223.72.67.117]) by esmtp4.qq.com (ESMTP) with id ; Sat, 19 Sep 2015 07:41:55 +0800 (CST) X-QQ-SSF: 01000000000000F0FG500F00002000H X-QQ-FEAT: rhtKA7lzEijj9jkgB28U42bJzl2M6DjoN0D0A0/dnU4XdtfymelEl5WCOtRWV H3XtatJxhmhXPwSee9lm+4Asg9gHvGrDT4vlp33my/fVuLCxRbbjAuUHBQP3ksOCH5sM53X qsrNew47Iszyaj0cvNo6eis5CVYoVy99Hkb8UUTwxEwILxjgIx0s0gGeTWnA4TgWJadfRTW o1yztsJXeWTNTUp/Xua8CcvWvcf8JBvZ6FKgX7gY5g+EWBbIPfPNM X-QQ-GoodBg: 0 X-QQ-CSender: gang.chen.5i5j@qq.com From: gang.chen.5i5j@gmail.com To: peter.maydell@linaro.org, rth@twiddle.net Date: Sat, 19 Sep 2015 07:41:47 +0800 Message-Id: <1442619707-3822-1-git-send-email-gang.chen.5i5j@gmail.com> X-Mailer: git-send-email 1.9.3 X-QQ-SENDSIZE: 520 X-QQ-FName: EA6F29E3F31C4E36BB7AA0ADE6C2CE61 X-QQ-LocalIP: 127.0.0.1 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 184.105.67.99 Cc: qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com, Chen Gang Subject: [Qemu-devel] [PATCH] target-tilegx: Implement v*shl, v*shru, and v*shrs instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Chen Gang Only according to the v1shl, v1shru, and v1shrs implementations. Signed-off-by: Chen Gang --- target-tilegx/helper.h | 6 +++++ target-tilegx/simd_helper.c | 62 +++++++++++++++++++++++++++++++++++++++++++++ target-tilegx/translate.c | 20 +++++++++++++++ 3 files changed, 88 insertions(+) diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h index 766f5f2..15093973 100644 --- a/target-tilegx/helper.h +++ b/target-tilegx/helper.h @@ -8,3 +8,9 @@ DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v4shl, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v4shru, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(v4shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c index b931929..6546337 100644 --- a/target-tilegx/simd_helper.c +++ b/target-tilegx/simd_helper.c @@ -32,6 +32,24 @@ uint64_t helper_v1shl(uint64_t a, uint64_t b) return (a & m) << b; } +uint64_t helper_v2shl(uint64_t a, uint64_t b) +{ + uint64_t m; + + b &= 15; + m = 0x0001000100010001ULL * (0xffff >> b); + return (a & m) << b; +} + +uint64_t helper_v4shl(uint64_t a, uint64_t b) +{ + uint64_t m; + + b &= 63; + m = 0x0000000100000001ULL * (0xffffffff >> b); + return (a & m) << b; +} + uint64_t helper_v1shru(uint64_t a, uint64_t b) { uint64_t m; @@ -41,6 +59,24 @@ uint64_t helper_v1shru(uint64_t a, uint64_t b) return (a & m) >> b; } +uint64_t helper_v2shru(uint64_t a, uint64_t b) +{ + uint64_t m; + + b &= 15; + m = 0x0001000100010001ULL * ((0xffff << b) & 0xffff); + return (a & m) >> b; +} + +uint64_t helper_v4shru(uint64_t a, uint64_t b) +{ + uint64_t m; + + b &= 63; + m = 0x0000000100000001ULL * ((0xffffffff << b) & 0xffffffff); + return (a & m) >> b; +} + uint64_t helper_v1shrs(uint64_t a, uint64_t b) { uint64_t r = 0; @@ -53,3 +89,29 @@ uint64_t helper_v1shrs(uint64_t a, uint64_t b) } return r; } + +uint64_t helper_v2shrs(uint64_t a, uint64_t b) +{ + uint64_t r = 0; + int i; + + b &= 15; + for (i = 0; i < 64; i += 16) { + int64_t ae = (int16_t)(a >> i); + r |= ((ae >> b) & 0xffff) << i; + } + return r; +} + +uint64_t helper_v4shrs(uint64_t a, uint64_t b) +{ + uint64_t r = 0; + int i; + + b &= 63; + for (i = 0; i < 64; i += 32) { + int64_t ae = (int32_t)(a >> i); + r |= ((ae >> b) & 0xffffffff) << i; + } + return r; +} diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index e70c3e5..c8247ac 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -1144,12 +1144,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(V2SADU, 0, X0): case OE_RRR(V2SHLSC, 0, X0): case OE_RRR(V2SHLSC, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V2SHL, 0, X0): case OE_RRR(V2SHL, 0, X1): + gen_helper_v2shl(tdest, tsrca, tsrcb); + mnemonic = "v2shl"; + break; case OE_RRR(V2SHRS, 0, X0): case OE_RRR(V2SHRS, 0, X1): + gen_helper_v2shrs(tdest, tsrca, tsrcb); + mnemonic = "v2shrs"; + break; case OE_RRR(V2SHRU, 0, X0): case OE_RRR(V2SHRU, 0, X1): + gen_helper_v2shru(tdest, tsrca, tsrcb); + mnemonic = "v2shru"; + break; case OE_RRR(V2SUBSC, 0, X0): case OE_RRR(V2SUBSC, 0, X1): case OE_RRR(V2SUB, 0, X0): @@ -1174,12 +1184,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(V4PACKSC, 0, X1): case OE_RRR(V4SHLSC, 0, X0): case OE_RRR(V4SHLSC, 0, X1): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(V4SHL, 0, X0): case OE_RRR(V4SHL, 0, X1): + gen_helper_v4shl(tdest, tsrca, tsrcb); + mnemonic = "v4shl"; + break; case OE_RRR(V4SHRS, 0, X0): case OE_RRR(V4SHRS, 0, X1): + gen_helper_v4shrs(tdest, tsrca, tsrcb); + mnemonic = "v4shrs"; + break; case OE_RRR(V4SHRU, 0, X0): case OE_RRR(V4SHRU, 0, X1): + gen_helper_v4shru(tdest, tsrca, tsrcb); + mnemonic = "v4shru"; + break; case OE_RRR(V4SUBSC, 0, X0): case OE_RRR(V4SUBSC, 0, X1): case OE_RRR(V4SUB, 0, X0):