From patchwork Fri Aug 21 05:05:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Guangrong X-Patchwork-Id: 509301 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 14474140772 for ; Fri, 21 Aug 2015 15:11:38 +1000 (AEST) Received: from localhost ([::1]:39828 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZSec3-0003zA-OT for incoming@patchwork.ozlabs.org; Fri, 21 Aug 2015 01:11:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZSebg-0003fp-KU for qemu-devel@nongnu.org; Fri, 21 Aug 2015 01:11:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZSebb-0004IQ-Ia for qemu-devel@nongnu.org; Fri, 21 Aug 2015 01:11:12 -0400 Received: from mga11.intel.com ([192.55.52.93]:38160) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZSebb-0004I6-DU for qemu-devel@nongnu.org; Fri, 21 Aug 2015 01:11:07 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 20 Aug 2015 22:11:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,719,1432623600"; d="scan'208";a="772899551" Received: from xiao.sh.intel.com ([10.239.159.86]) by fmsmga001.fm.intel.com with ESMTP; 20 Aug 2015 22:11:03 -0700 From: Xiao Guangrong To: pbonzini@redhat.com, imammedo@redhat.com Date: Fri, 21 Aug 2015 13:05:12 +0800 Message-Id: <1440133512-28005-1-git-send-email-guangrong.xiao@linux.intel.com> X-Mailer: git-send-email 2.4.3 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.93 Cc: Xiao Guangrong , ehabkost@redhat.com, kvm@vger.kernel.org, mst@redhat.com, gleb@kernel.org, mtosatti@redhat.com, qemu-devel@nongnu.org, stefanha@redhat.com, rth@twiddle.net Subject: [Qemu-devel] [PATCH] target-i386: enable cflushopt/clwb/pcommit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org These instructions are used by NVDIMM drivers and the specification locates at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf Let them be enabled on Broadwell on default Signed-off-by: Xiao Guangrong --- target-i386/cpu.c | 14 +++++++++----- target-i386/cpu.h | 3 +++ 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 7a779b1..2129b3a 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -260,8 +260,8 @@ static const char *svm_feature_name[] = { static const char *cpuid_7_0_ebx_feature_name[] = { "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep", "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL, - "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL, - NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL, + "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt", + "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL, }; static const char *cpuid_apm_edx_feature_name[] = { @@ -346,7 +346,9 @@ static const char *cpuid_6_feature_name[] = { #define TCG_SVM_FEATURES 0 #define TCG_KVM_FEATURES 0 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ - CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX) + CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ + CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ + CPUID_7_0_EBX_CLWB) /* missing: CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, @@ -1191,7 +1193,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | - CPUID_7_0_EBX_SMAP, + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_PCOMMIT | + CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = @@ -1229,7 +1232,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | - CPUID_7_0_EBX_SMAP, + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_PCOMMIT | + CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, .features[FEAT_6_EAX] = diff --git a/target-i386/cpu.h b/target-i386/cpu.h index ead2832..cb65c05 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -572,6 +572,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_RDSEED (1U << 18) #define CPUID_7_0_EBX_ADX (1U << 19) #define CPUID_7_0_EBX_SMAP (1U << 20) +#define CPUID_7_0_EBX_PCOMMIT (1 << 22) +#define CPUID_7_0_EBX_CLFLUSHOPT (1 << 23) +#define CPUID_7_0_EBX_CLWB (1 << 24) #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */