From patchwork Sun Aug 9 20:13:22 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 505453 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 794C31401C7 for ; Mon, 10 Aug 2015 06:16:49 +1000 (AEST) Received: from localhost ([::1]:56123 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZOX1T-0005U8-JG for incoming@patchwork.ozlabs.org; Sun, 09 Aug 2015 16:16:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52054) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZOWyz-0000UH-5k for qemu-devel@nongnu.org; Sun, 09 Aug 2015 16:14:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZOWyw-0005MK-0d for qemu-devel@nongnu.org; Sun, 09 Aug 2015 16:14:13 -0400 Received: from smtp4-g21.free.fr ([2a01:e0c:1:1599::13]:2395) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZOWyv-0005Lt-Nn for qemu-devel@nongnu.org; Sun, 09 Aug 2015 16:14:09 -0400 Received: from Quad.localdomain (unknown [78.238.229.36]) by smtp4-g21.free.fr (Postfix) with ESMTPS id 6292C4C8089; Sun, 9 Aug 2015 22:14:08 +0200 (CEST) From: Laurent Vivier To: qemu-devel@nongnu.org Date: Sun, 9 Aug 2015 22:13:22 +0200 Message-Id: <1439151229-27747-4-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1439151229-27747-1-git-send-email-laurent@vivier.eu> References: <1439151229-27747-1-git-send-email-laurent@vivier.eu> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a01:e0c:1:1599::13 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Andreas Schwab , Laurent Vivier , gerg@uclinux.org Subject: [Qemu-devel] [PATCH for-2.5 03/30] m68k: introduce read_imXX() functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Read a 8, 16 or 32bit immediat constant. An Immediat constant is stored in the instruction opcode and can be in one or two extension words. Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 73 ++++++++++++++++++++++++------------------------- 1 file changed, 35 insertions(+), 38 deletions(-) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index f190f19..3b87b0c 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -260,16 +260,30 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, } } -/* Read a 32-bit immediate constant. */ -static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) +/* Read an 8-bit immediate constant */ +static inline uint32_t read_im8(CPUM68KState *env, DisasContext *s) { uint32_t im; - im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16; + im = cpu_ldsb_code(env, s->pc + 1); s->pc += 2; - im |= cpu_lduw_code(env, s->pc); + return im; +} +/* Read a 16-bit immediate constant */ +static inline uint32_t read_im16(CPUM68KState *env, DisasContext *s) +{ + uint32_t im; + im = cpu_ldsw_code(env, s->pc); s->pc += 2; return im; } +/* Read a 32-bit immediate constant. */ +static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) +{ + uint32_t im; + im = read_im16(env, s) << 16; + im |= 0xffff & read_im16(env, s); + return im; +} /* Calculate and address index. */ static TCGv gen_addr_index(uint16_t ext, TCGv tmp) @@ -301,8 +315,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) uint32_t bd, od; offset = s->pc; - ext = cpu_lduw_code(env, s->pc); - s->pc += 2; + ext = read_im16(env, s); if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) return NULL_QREG; @@ -320,8 +333,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) if ((ext & 0x30) > 0x10) { /* base displacement */ if ((ext & 0x30) == 0x20) { - bd = (int16_t)cpu_lduw_code(env, s->pc); - s->pc += 2; + bd = (int16_t)read_im16(env, s); } else { bd = read_im32(env, s); } @@ -369,8 +381,7 @@ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) if ((ext & 3) > 1) { /* outer displacement */ if ((ext & 3) == 2) { - od = (int16_t)cpu_lduw_code(env, s->pc); - s->pc += 2; + od = (int16_t)read_im16(env, s); } else { od = read_im32(env, s); } @@ -522,8 +533,7 @@ static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, case 5: /* Indirect displacement. */ reg = AREG(insn, 0); tmp = tcg_temp_new(); - ext = cpu_lduw_code(env, s->pc); - s->pc += 2; + ext = read_im16(env, s); tcg_gen_addi_i32(tmp, reg, (int16_t)ext); return tmp; case 6: /* Indirect index + displacement. */ @@ -947,8 +957,7 @@ DISAS_INSN(divl) TCGv reg; uint16_t ext; - ext = cpu_lduw_code(env, s->pc); - s->pc += 2; + ext = read_im16(env, s); if (ext & 0x87f8) { gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); return; @@ -1099,8 +1108,7 @@ DISAS_INSN(movem) TCGv tmp; int is_load; - mask = cpu_lduw_code(env, s->pc); - s->pc += 2; + mask = read_im16(env, s); tmp = gen_lea(env, s, insn, OS_LONG); if (IS_NULL_QREG(tmp)) { gen_addr_fault(s); @@ -1143,8 +1151,7 @@ DISAS_INSN(bitop_im) opsize = OS_LONG; op = (insn >> 6) & 3; - bitnum = cpu_lduw_code(env, s->pc); - s->pc += 2; + bitnum = read_im16(env, s); if (bitnum & 0xff00) { disas_undef(env, s, insn); return; @@ -1397,8 +1404,7 @@ static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, else if ((insn & 0x3f) == 0x3c) { uint16_t val; - val = cpu_lduw_code(env, s->pc); - s->pc += 2; + val = read_im16(env, s); gen_set_sr_im(s, val, ccr_only); } else @@ -1521,8 +1527,7 @@ DISAS_INSN(mull) /* The upper 32 bits of the product are discarded, so muls.l and mulu.l are functionally equivalent. */ - ext = cpu_lduw_code(env, s->pc); - s->pc += 2; + ext = read_im16(env, s); if (ext & 0x87ff) { gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); return; @@ -1948,14 +1953,12 @@ DISAS_INSN(strldsr) uint32_t addr; addr = s->pc - 2; - ext = cpu_lduw_code(env, s->pc); - s->pc += 2; + ext = read_im16(env, s); if (ext != 0x46FC) { gen_exception(s, addr, EXCP_UNSUPPORTED); return; } - ext = cpu_lduw_code(env, s->pc); - s->pc += 2; + ext = read_im16(env, s); if (IS_USER(s) || (ext & SR_S) == 0) { gen_exception(s, addr, EXCP_PRIVILEGE); return; @@ -2022,8 +2025,7 @@ DISAS_INSN(stop) return; } - ext = cpu_lduw_code(env, s->pc); - s->pc += 2; + ext = read_im16(env, s); gen_set_sr_im(s, ext, 0); tcg_gen_movi_i32(cpu_halted, 1); @@ -2049,8 +2051,7 @@ DISAS_INSN(movec) return; } - ext = cpu_lduw_code(env, s->pc); - s->pc += 2; + ext = read_im16(env, s); if (ext & 0x8000) { reg = AREG(ext, 12); @@ -2116,8 +2117,7 @@ DISAS_INSN(fpu) int set_dest; int opsize; - ext = cpu_lduw_code(env, s->pc); - s->pc += 2; + ext = read_im16(env, s); opmode = ext & 0x7f; switch ((ext >> 13) & 7) { case 0: case 2: @@ -2399,8 +2399,7 @@ DISAS_INSN(fbcc) offset = cpu_ldsw_code(env, s->pc); s->pc += 2; if (insn & (1 << 6)) { - offset = (offset << 16) | cpu_lduw_code(env, s->pc); - s->pc += 2; + offset = (offset << 16) | read_im16(env, s); } l1 = gen_new_label(); @@ -2525,8 +2524,7 @@ DISAS_INSN(mac) s->done_mac = 1; } - ext = cpu_lduw_code(env, s->pc); - s->pc += 2; + ext = read_im16(env, s); acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); dual = ((insn & 0x30) != 0 && (ext & 3) != 0); @@ -3034,8 +3032,7 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) tcg_gen_debug_insn_start(s->pc); } - insn = cpu_lduw_code(env, s->pc); - s->pc += 2; + insn = read_im16(env, s); opcode_table[insn](env, s, insn); }