From patchwork Sun Aug 9 20:13:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 505475 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 98653140321 for ; Mon, 10 Aug 2015 06:28:02 +1000 (AEST) Received: from localhost ([::1]:56240 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZOXCK-0002Ls-Mf for incoming@patchwork.ozlabs.org; Sun, 09 Aug 2015 16:28:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZOWz7-0000iR-DA for qemu-devel@nongnu.org; Sun, 09 Aug 2015 16:14:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZOWz4-0005St-V6 for qemu-devel@nongnu.org; Sun, 09 Aug 2015 16:14:21 -0400 Received: from smtp4-g21.free.fr ([2a01:e0c:1:1599::13]:3042) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZOWz4-0005Sg-OV for qemu-devel@nongnu.org; Sun, 09 Aug 2015 16:14:18 -0400 Received: from Quad.localdomain (unknown [78.238.229.36]) by smtp4-g21.free.fr (Postfix) with ESMTPS id 19D0C4C8097; Sun, 9 Aug 2015 22:14:18 +0200 (CEST) From: Laurent Vivier To: qemu-devel@nongnu.org Date: Sun, 9 Aug 2015 22:13:43 +0200 Message-Id: <1439151229-27747-25-git-send-email-laurent@vivier.eu> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1439151229-27747-1-git-send-email-laurent@vivier.eu> References: <1439151229-27747-1-git-send-email-laurent@vivier.eu> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a01:e0c:1:1599::13 Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, Andreas Schwab , Laurent Vivier , gerg@uclinux.org Subject: [Qemu-devel] [PATCH for-2.5 24/30] m68k: add DBcc and Scc (memory operand) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Laurent Vivier --- target-m68k/translate.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 95d58d1..cb746d7 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -994,6 +994,50 @@ static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) s->is_jmp = DISAS_TB_JUMP; } +DISAS_INSN(scc_mem) +{ + TCGLabel *l1; + int cond; + TCGv dest; + + l1 = gen_new_label(); + cond = (insn >> 8) & 0xf; + dest = tcg_temp_local_new(); + tcg_gen_movi_i32(dest, 0); + gen_jmpcc(s, cond ^ 1, l1); + tcg_gen_movi_i32(dest, 0xff); + gen_set_label(l1); + DEST_EA(env, insn, OS_BYTE, dest, NULL); + tcg_temp_free(dest); +} + +DISAS_INSN(dbcc) +{ + TCGLabel *l1; + TCGv reg; + TCGv tmp; + int16_t offset; + uint32_t base; + + reg = DREG(insn, 0); + base = s->pc; + offset = cpu_ldsw_code(env, s->pc); + s->pc += 2; + l1 = gen_new_label(); + gen_jmpcc(s, (insn >> 8) & 0xf, l1); + + tmp = tcg_temp_new(); + tcg_gen_ext16s_i32(tmp, reg); + tcg_gen_addi_i32(tmp, tmp, -1); + gen_partset_reg(OS_WORD, reg, tmp); + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1); + update_cc_op(s); + gen_jmp_tb(s, 1, base + offset); + gen_set_label(l1); + update_cc_op(s); + gen_jmp_tb(s, 0, s->pc); +} + DISAS_INSN(undef_mac) { gen_exception(s, s->pc - 2, EXCP_LINEA); @@ -3248,6 +3292,9 @@ void register_m68k_insns (CPUM68KState *env) INSN(addsubq, 5080, f0c0, M68000); INSN(scc, 50c0, f0f8, CF_ISA_A); INSN(addsubq, 5080, f1c0, CF_ISA_A); + INSN(scc_mem, 50c0, f0c0, M68000); + INSN(scc, 50c0, f0f8, M68000); + INSN(dbcc, 50c8, f0f8, M68000); INSN(tpf, 51f8, fff8, CF_ISA_A); /* Branch instructions. */