From patchwork Wed Aug 5 16:51:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 504095 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8D6631402B8 for ; Thu, 6 Aug 2015 02:53:54 +1000 (AEST) Received: from localhost ([::1]:41259 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZN1wu-00030n-Je for incoming@patchwork.ozlabs.org; Wed, 05 Aug 2015 12:53:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37580) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZN1uz-0001k3-Or for qemu-devel@nongnu.org; Wed, 05 Aug 2015 12:51:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZN1uy-0004tf-I2 for qemu-devel@nongnu.org; Wed, 05 Aug 2015 12:51:53 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55195) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZN1uy-0004tX-9n for qemu-devel@nongnu.org; Wed, 05 Aug 2015 12:51:52 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id C00611409F2; Wed, 5 Aug 2015 16:51:51 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id A223F1409F5; Wed, 5 Aug 2015 16:51:51 +0000 (UTC) Received: from keeshans.qualcomm.com (rrcs-67-52-130-30.west.biz.rr.com [67.52.130.30]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 609F61409F2; Wed, 5 Aug 2015 16:51:50 +0000 (UTC) From: Christopher Covington To: qemu-devel@nongnu.org Date: Wed, 5 Aug 2015 12:51:13 -0400 Message-Id: <1438793483-12721-5-git-send-email-cov@codeaurora.org> X-Mailer: git-send-email 1.8.1.1 In-Reply-To: <1438793483-12721-1-git-send-email-cov@codeaurora.org> References: <1438793483-12721-1-git-send-email-cov@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 198.145.29.96 Cc: Christopher Covington Subject: [Qemu-devel] [RFC 04/14] Modify load exclusive/store exclusive to use physical addresses with the monitor X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Written by Derek Hower. Signed-off-by: Christopher Covington --- target-arm/helper-a64.h | 2 ++ target-arm/helper.c | 22 ++++++++++++++++++++++ target-arm/translate-a64.c | 25 +++++++++++++++++++++++-- 3 files changed, 47 insertions(+), 2 deletions(-) diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h index 1d3d10f..a713d29 100644 --- a/target-arm/helper-a64.h +++ b/target-arm/helper-a64.h @@ -46,3 +46,5 @@ DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) + +DEF_HELPER_3(get_phys_addr64, i64, env, i64, i32) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4491b05..be564b2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -24,6 +24,28 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address, #define PMCRE 0x1 #endif +#ifdef TARGET_AARCH64 + +uint64_t HELPER(get_phys_addr64)(CPUARMState *env, + uint64_t vaddr, uint32_t memidx) +{ +#ifdef CONFIG_USER_ONLY + return vaddr; +#else + hwaddr phys_addr; + int prot; // ignored + target_ulong page_size; // ignored + MemTxAttrs attrs = {}; // ignored + + // we just want the address from this function and don't care about faults. + // therefore, we always assume the operation is a load + get_phys_addr(env, vaddr, 0, memidx == 0, &phys_addr, &attrs, &prot, &page_size); + return phys_addr; +#endif +} + +#endif + static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { int nregs; diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 14a501c..20d1d3c 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1683,7 +1683,17 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, tcg_gen_mov_i64(cpu_reg(s, rt), tmp); tcg_temp_free_i64(tmp); - tcg_gen_mov_i64(cpu_exclusive_addr, addr); + + // the monitor must be set on the physical address + // we've already read the address at this point, so we know + // the translation won't fault + TCGv_i64 physaddr = tcg_temp_new_i64(); + TCGv_i32 idx = tcg_temp_new_i32(); + tcg_gen_movi_i32(idx, get_mem_index(s)); + gen_helper_get_phys_addr64(physaddr, cpu_env, addr, idx); + tcg_gen_mov_i64(cpu_exclusive_addr, physaddr); + tcg_temp_free_i64(physaddr); + tcg_temp_free_i32(idx); } #ifdef CONFIG_USER_ONLY @@ -1720,13 +1730,24 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, * basic block ends at the branch insn. */ tcg_gen_mov_i64(addr, inaddr); - tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); tmp = tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), MO_TE + size); tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label); tcg_temp_free_i64(tmp); + // the monitor must be checked on the physical address. + // We've alredy loaded this address, so we don't need to check for + // a fault condition + TCGv_i64 physaddr = tcg_temp_new_i64(); + TCGv_i32 idx = tcg_temp_new_i32(); + tcg_gen_movi_i32(idx, get_mem_index(s)); + gen_helper_get_phys_addr64(physaddr, cpu_env, addr, idx); + + tcg_gen_brcond_i64(TCG_COND_NE, physaddr, cpu_exclusive_addr, fail_label); + tcg_temp_free_i64(physaddr); + tcg_temp_free_i32(idx); + if (is_pair) { TCGv_i64 addrhi = tcg_temp_new_i64(); TCGv_i64 tmphi = tcg_temp_new_i64();