From patchwork Wed Aug 5 16:51:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 504168 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 30E591402B8 for ; Thu, 6 Aug 2015 04:35:09 +1000 (AEST) Received: from localhost ([::1]:41278 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZN1yQ-0003t5-8A for incoming@patchwork.ozlabs.org; Wed, 05 Aug 2015 12:55:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37644) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZN1v9-00021y-IC for qemu-devel@nongnu.org; Wed, 05 Aug 2015 12:52:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZN1v6-0004vp-Em for qemu-devel@nongnu.org; Wed, 05 Aug 2015 12:52:03 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55227) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZN1v6-0004vl-7N for qemu-devel@nongnu.org; Wed, 05 Aug 2015 12:52:00 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id B96A4140A16; Wed, 5 Aug 2015 16:51:59 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id 9BB18140A19; Wed, 5 Aug 2015 16:51:59 +0000 (UTC) Received: from keeshans.qualcomm.com (rrcs-67-52-130-30.west.biz.rr.com [67.52.130.30]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 976E9140A16; Wed, 5 Aug 2015 16:51:58 +0000 (UTC) From: Christopher Covington To: qemu-devel@nongnu.org Date: Wed, 5 Aug 2015 12:51:19 -0400 Message-Id: <1438793483-12721-11-git-send-email-cov@codeaurora.org> X-Mailer: git-send-email 1.8.1.1 In-Reply-To: <1438793483-12721-1-git-send-email-cov@codeaurora.org> References: <1438793483-12721-1-git-send-email-cov@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 198.145.29.96 Cc: Christopher Covington Subject: [Qemu-devel] [RFC 10/14] bbvec: Move mode/PID change detection to register writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This should speed up basic block detection since these were previously being checked for on each basic block / instruction. Written by Aaron Lindsay. Signed-off-by: Christopher Covington --- target-arm/cpu.h | 13 +++++++++++++ target-arm/helper-a64.c | 2 +- target-arm/helper.c | 39 +++++++++++++++++++++++++++++---------- target-arm/helper.h | 2 -- target-arm/translate-a64.c | 2 -- target-arm/translate.c | 2 -- 6 files changed, 43 insertions(+), 17 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f6857fa..6c4ba9c 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -670,14 +670,27 @@ static inline uint32_t pstate_read(CPUARMState *env) | env->pstate | env->daif; } +void update_instruction_count(CPUARMState *env); +#ifdef CONFIG_BBVEC +void context_check_mode(CPUARMState *env); +#endif + static inline void pstate_write(CPUARMState *env, uint32_t val) { + bool mode_changed = (env->pstate ^ val) & PSTATE_M; env->ZF = (~val) & PSTATE_Z; env->NF = val; env->CF = (val >> 29) & 1; env->VF = (val << 3) & 0x80000000; env->daif = val & PSTATE_DAIF; env->pstate = val & ~CACHED_PSTATE_BITS; + + if (mode_changed) { + update_instruction_count(env); +#ifdef CONFIG_BBVEC + context_check_mode(env); +#endif + } } /* Return the current CPSR value. */ diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 8803293..e647b90 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -558,8 +558,8 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->condexec_bits = 0; } - pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; + pstate_write(env, PSTATE_DAIF | new_mode); aarch64_restore_sp(env, new_el); env->pc = addr; diff --git a/target-arm/helper.c b/target-arm/helper.c index a659e67..c1f4c47 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -387,6 +387,7 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) } } +void context_check_pid(CPUARMState *env); static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -399,6 +400,9 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, arm_tlb_flush(env, 1); } raw_write(env, ri, value); +#ifdef CONFIG_BBVEC + context_check_pid(env); +#endif } static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4292,29 +4296,34 @@ void HELPER(bbv_profile)(CPUARMState *env) } } -void HELPER(context_check_mode)(CPUARMState *env) +void context_check_mode(CPUARMState *env) { - uint32_t mode; + uint32_t priv_mode; /* nonzero if privileged */ + + if (!bbtrace_initialized()) + return; - /* Get current mode: userspace or privileged */ if (env->aarch64) { - mode = extract32(env->pstate, 2, 2); + priv_mode = extract32(env->pstate, 2, 2); } else if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { - mode = 0; + priv_mode = 0; } /* We don't currently implement the Virtualization or TrustZone * extensions, so PL2 and PL3 don't exist for us. */ - else mode = 1; + else priv_mode = 1; - bb_context_check_mode(env->prof_ic, mode); + bb_context_check_mode(env->prof_ic, priv_mode); } -void HELPER(context_check_pid)(CPUARMState *env) +void context_check_pid(CPUARMState *env) { uint64_t pid; + if (!bbtrace_initialized()) + return; + /* Read pid from CONTEXTIDR register. In aarch32, if EL1 is not in AArch64 * mode, we need to shift out the address space identifier in the first 8 bits. * @@ -4331,7 +4340,7 @@ void HELPER(context_check_pid)(CPUARMState *env) bb_context_check_pid(env->prof_ic, pid); } -void HELPER(update_instruction_count)(CPUARMState *env) +void update_instruction_count(CPUARMState *env) { if (bbtrace_initialized()) { /* @@ -4360,7 +4369,7 @@ void HELPER(update_instruction_count)(CPUARMState *env) #else //!CONFIG_BBVEC -void HELPER(update_instruction_count)(CPUARMState *env) +void update_instruction_count(CPUARMState *env) { pmevcntr_increment(env, PMU_COUNTER_TYPE_INSTRUCTIONS, env->prof_ic); pmevcntr_increment(env, PMU_COUNTER_TYPE_CYCLES, env->prof_ic); @@ -4369,6 +4378,11 @@ void HELPER(update_instruction_count)(CPUARMState *env) #endif //CONFIG_BBVEC +void HELPER(update_instruction_count)(CPUARMState *env) +{ + update_instruction_count(env); +} + /* Sign/zero extend */ uint32_t HELPER(sxtb16)(uint32_t x) { @@ -4525,6 +4539,11 @@ void switch_mode(CPUARMState *env, int mode) if (mode == old_mode) return; + update_instruction_count(env); +#ifdef CONFIG_BBVEC + context_check_mode(env); +#endif + if (old_mode == ARM_CPU_MODE_FIQ) { memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); diff --git a/target-arm/helper.h b/target-arm/helper.h index 02edf3a..0f88080 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -39,8 +39,6 @@ PAS_OP(uh) #ifdef CONFIG_BBVEC DEF_HELPER_1(bbv_profile, void, env) -DEF_HELPER_1(context_check_mode, void, env) -DEF_HELPER_1(context_check_pid, void, env) #endif // CONFIG_BBVEC DEF_HELPER_1(update_instruction_count, void, env) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index f6f8832..2471184 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -11076,14 +11076,12 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, if (bbtrace_initialized()) { gen_helper_bbv_profile(cpu_env); gen_store_is_jmp(0); - gen_helper_context_check_pid(cpu_env); } #endif // CONFIG_BBVEC do { #ifdef CONFIG_BBVEC if (bbtrace_initialized()) { - gen_helper_context_check_mode(cpu_env); gen_pc_incr(env, dc); } #endif // CONFIG_BBVEC diff --git a/target-arm/translate.c b/target-arm/translate.c index 113e3b6..f9d69ef 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11635,14 +11635,12 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, if (bbtrace_initialized()) { gen_helper_bbv_profile(cpu_env); gen_store_is_jmp(0); - gen_helper_context_check_pid(cpu_env); } #endif do { #ifdef CONFIG_BBVEC if (bbtrace_initialized()) { - gen_helper_context_check_mode(cpu_env); gen_pc_incr(env, dc); /* FIXME: this call should not be necessary if all the cases where the prof_is_jmp flag gets set are correct. */