From patchwork Wed Jun 3 21:09:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 480225 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D02DC1402B1 for ; Thu, 4 Jun 2015 07:15:31 +1000 (AEST) Received: from localhost ([::1]:38241 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0G0X-00038l-Tt for incoming@patchwork.ozlabs.org; Wed, 03 Jun 2015 17:15:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60484) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0FvL-0001OO-8i for qemu-devel@nongnu.org; Wed, 03 Jun 2015 17:10:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0FvI-0007t0-FB for qemu-devel@nongnu.org; Wed, 03 Jun 2015 17:10:07 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:40097) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0FvI-0007rB-AF for qemu-devel@nongnu.org; Wed, 03 Jun 2015 17:10:04 -0400 Received: from weber.rr44.fr ([2001:470:d4ed:0:7e05:7ff:fe0d:f152]) by hall.aurel32.net with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84) (envelope-from ) id 1Z0FvG-0003Wo-El; Wed, 03 Jun 2015 23:10:02 +0200 Received: from aurel32 by weber.rr44.fr with local (Exim 4.85) (envelope-from ) id 1Z0FvF-0000QM-9x; Wed, 03 Jun 2015 23:10:01 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 3 Jun 2015 23:09:54 +0200 Message-Id: <1433365796-1118-15-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1433365796-1118-1-git-send-email-aurelien@aurel32.net> References: <1433365796-1118-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:101::1 Cc: Alexander Graf , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH v2 14/16] target-s390x: support non current ASC in s390_cpu_handle_mmu_fault X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org s390_cpu_handle_mmu_fault currently looks at the current ASC mode defined in PSW mask instead of the MMU index. This prevent emulating easily instructions using a specific ASC mode. Fix that by using the MMU index converted back to ASC using the just added cpu_mmu_idx_to_asc function. Cc: Alexander Graf Cc: Richard Henderson Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target-s390x/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-s390x/helper.c b/target-s390x/helper.c index 6b47766..90d273c 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -112,7 +112,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, { S390CPU *cpu = S390_CPU(cs); CPUS390XState *env = &cpu->env; - uint64_t asc = env->psw.mask & PSW_MASK_ASC; + uint64_t asc = cpu_mmu_idx_to_asc(mmu_idx); target_ulong vaddr, raddr; int prot;