From patchwork Sun May 24 23:47:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 476031 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1BFF01402B9 for ; Mon, 25 May 2015 09:50:23 +1000 (AEST) Received: from localhost ([::1]:41214 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ywfeu-00083Q-W5 for incoming@patchwork.ozlabs.org; Sun, 24 May 2015 19:50:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58304) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwfcM-00038n-17 for qemu-devel@nongnu.org; Sun, 24 May 2015 19:47:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YwfcJ-00081E-Ar for qemu-devel@nongnu.org; Sun, 24 May 2015 19:47:41 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:40638) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwfcJ-00080E-4w for qemu-devel@nongnu.org; Sun, 24 May 2015 19:47:39 -0400 Received: from weber.rr44.fr ([2001:470:d4ed:0:7e05:7ff:fe0d:f152]) by hall.aurel32.net with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84) (envelope-from ) id 1YwfcG-0006oI-S8; Mon, 25 May 2015 01:47:37 +0200 Received: from aurel32 by weber.rr44.fr with local (Exim 4.85) (envelope-from ) id 1YwfcF-0005tX-Uw; Mon, 25 May 2015 01:47:35 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 25 May 2015 01:47:30 +0200 Message-Id: <1432511251-22515-10-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1432511251-22515-1-git-send-email-aurelien@aurel32.net> References: <1432511251-22515-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:101::1 Cc: Alexander Graf , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH 09/10] target-s390x: move a few instructions to the correct facility X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org LY is part of the long-displacement facility. RISBHG and RISBLG are part of the high-word facility. STCMH is part of the z/Architecture. Cc: Alexander Graf Cc: Richard Henderson Signed-off-by: Aurelien Jarno --- target-s390x/insn-data.def | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index fd45730..d57ce32 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -336,7 +336,7 @@ /* LOAD */ C(0x1800, LR, RR_a, Z, 0, r2_o, 0, cond_r1r2_32, mov2, 0) C(0x5800, L, RX_a, Z, 0, a2, new, r1_32, ld32s, 0) - C(0xe358, LY, RXY_a, Z, 0, a2, new, r1_32, ld32s, 0) + C(0xe358, LY, RXY_a, LD, 0, a2, new, r1_32, ld32s, 0) C(0xb904, LGR, RRE, Z, 0, r2_o, 0, r1, mov2, 0) C(0xb914, LGFR, RRE, Z, 0, r2_32s, 0, r1, mov2, 0) C(0xe304, LG, RXY_a, Z, 0, a2, r1, 0, ld64, 0) @@ -595,8 +595,8 @@ /* ROTATE THEN INSERT SELECTED BITS */ C(0xec55, RISBG, RIE_f, GIE, 0, r2, r1, 0, risbg, s64) - C(0xec5d, RISBHG, RIE_f, GIE, 0, r2, r1, 0, risbg, 0) - C(0xec51, RISBLG, RIE_f, GIE, 0, r2, r1, 0, risbg, 0) + C(0xec5d, RISBHG, RIE_f, HW, 0, r2, r1, 0, risbg, 0) + C(0xec51, RISBLG, RIE_f, HW, 0, r2, r1, 0, risbg, 0) /* ROTATE_THEN SELECTED BITS */ C(0xec54, RNSBG, RIE_f, GIE, 0, r2, r1, 0, rosbg, 0) C(0xec56, ROSBG, RIE_f, GIE, 0, r2, r1, 0, rosbg, 0) @@ -670,7 +670,7 @@ /* STORE CHARACTERS UNDER MASK */ D(0xbe00, STCM, RS_b, Z, r1_o, a2, 0, 0, stcm, 0, 0) D(0xeb2d, STCMY, RSY_b, LD, r1_o, a2, 0, 0, stcm, 0, 0) - D(0xeb2c, STCMH, RSY_b, LD, r1_o, a2, 0, 0, stcm, 0, 32) + D(0xeb2c, STCMH, RSY_b, Z, r1_o, a2, 0, 0, stcm, 0, 32) /* STORE HALFWORD */ C(0x4000, STH, RX_a, Z, r1_o, a2, 0, 0, st16, 0) C(0xe370, STHY, RXY_a, LD, r1_o, a2, 0, 0, st16, 0)