From patchwork Wed May 20 01:58:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 474119 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4A3B3140D4E for ; Wed, 20 May 2015 11:59:19 +1000 (AEST) Received: from localhost ([::1]:49537 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YutHw-000755-Gn for incoming@patchwork.ozlabs.org; Tue, 19 May 2015 21:59:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YutHg-0006oR-BO for qemu-devel@nongnu.org; Tue, 19 May 2015 21:59:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YutHc-000371-Sw for qemu-devel@nongnu.org; Tue, 19 May 2015 21:59:00 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:34499) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YutHc-00036q-Ny for qemu-devel@nongnu.org; Tue, 19 May 2015 21:58:56 -0400 Received: by pabru16 with SMTP id ru16so47894701pab.1 for ; Tue, 19 May 2015 18:58:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=D4uGBi5amCwv+dbcgQ6jVL2FYq8d5vS6CZhkFlEfmuc=; b=gT7cj9dMuUdxXMQJUe6vWF39xZQdTcADVdDD0WcwPS/YvFPvn2qxIymfThLbfCQ4bf MkHNZnAXRJCDaaWwKWKnXnbQIc6+T9xYiefXlh62mK3cMSdqucqmdiJZo7Q3Rrag1/Ac y0GNTGa4ZOO10DTqs3lxDke0ap/A63wOy+iPGia8q1JDv/+C7AWQx/EG8q9D8OMl+EZq kZcTe1SDVzuu8e/7y/5yJD4bgv3IEYnX+0c5QuYRo2c9oaXj4cDtQ3kZrjaKEUNFsQgi ZNvCC5lSAOB7uf86dHagnlM9ZdlyG2V68mwkswnWj0oqOiU8XZJDVfR/APVueHpgwh/7 +dNA== X-Gm-Message-State: ALoCoQmLLsrrc6Tc24r4yzLvfslKgRkVP9LUEwIVQVpvdwiq4itDqUBHbKP4J1impTWJ3kv2FYUU X-Received: by 10.68.204.36 with SMTP id kv4mr58287480pbc.37.1432087135474; Tue, 19 May 2015 18:58:55 -0700 (PDT) Received: from localhost ([180.150.152.123]) by mx.google.com with ESMTPSA id f4sm14295844pdc.95.2015.05.19.18.58.53 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 19 May 2015 18:58:54 -0700 (PDT) From: shannon.zhao@linaro.org To: qemu-devel@nongnu.org, mst@redhat.com Date: Wed, 20 May 2015 09:58:50 +0800 Message-Id: <1432087130-5264-1-git-send-email-shannon.zhao@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.47 Cc: peter.huangpeng@huawei.com, zhaoshenglong@huawei.com Subject: [Qemu-devel] [PATCH] hw/pci-bridge: Report an error when msi init fails X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Shannon Zhao Notice user the reason for device initialization failure. Signed-off-by: Shannon Zhao Signed-off-by: Shannon Zhao --- hw/pci-bridge/ioh3420.c | 2 ++ hw/pci-bridge/pci_bridge_dev.c | 2 ++ hw/pci-bridge/xio3130_downstream.c | 2 ++ hw/pci-bridge/xio3130_upstream.c | 2 ++ 4 files changed, 8 insertions(+) diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c index cce2fdd..458126a 100644 --- a/hw/pci-bridge/ioh3420.c +++ b/hw/pci-bridge/ioh3420.c @@ -24,6 +24,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "ioh3420.h" +#include "qemu/error-report.h" #define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */ #define PCI_DEVICE_ID_IOH_REV 0x2 @@ -113,6 +114,7 @@ static int ioh3420_initfn(PCIDevice *d) IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); if (rc < 0) { + error_report("Failed to initialize MSI, error %d", rc); goto err_bridge; } rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port); diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 36f73e1..114a205 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -27,6 +27,7 @@ #include "exec/memory.h" #include "hw/pci/pci_bus.h" #include "hw/hotplug.h" +#include "qemu/error-report.h" #define TYPE_PCI_BRIDGE_DEV "pci-bridge" #define PCI_BRIDGE_DEV(obj) \ @@ -68,6 +69,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev) msi_supported) { err = msi_init(dev, 0, 1, true, true); if (err < 0) { + error_report("Failed to initialize MSI, error %d", err); goto msi_error; } } diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index b3a6479..5eff0d8 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -23,6 +23,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "xio3130_downstream.h" +#include "qemu/error-report.h" #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */ #define XIO3130_REVISION 0x1 @@ -71,6 +72,7 @@ static int xio3130_downstream_initfn(PCIDevice *d) XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); if (rc < 0) { + error_report("Failed to initialize MSI, error %d", rc); goto err_bridge; } rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index eada582..8d045ec 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -23,6 +23,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "xio3130_upstream.h" +#include "qemu/error-report.h" #define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */ #define XIO3130_REVISION 0x2 @@ -67,6 +68,7 @@ static int xio3130_upstream_initfn(PCIDevice *d) XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); if (rc < 0) { + error_report("Failed to initialize MSI, error %d", rc); goto err_bridge; } rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,