From patchwork Tue May 5 09:13:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?SsOpcsOpbXkgRmFuZ3XDqGRl?= X-Patchwork-Id: 467966 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 13AE41409B7 for ; Tue, 5 May 2015 19:14:22 +1000 (AEST) Received: from localhost ([::1]:37751 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpYvj-0001qz-Rv for incoming@patchwork.ozlabs.org; Tue, 05 May 2015 05:14:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41723) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpYvF-0001Qs-Q8 for qemu-devel@nongnu.org; Tue, 05 May 2015 05:14:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YpYvA-0007GA-NP for qemu-devel@nongnu.org; Tue, 05 May 2015 05:13:49 -0400 Received: from mail-wi0-f176.google.com ([209.85.212.176]:36404) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpYvA-0007Fv-HV for qemu-devel@nongnu.org; Tue, 05 May 2015 05:13:44 -0400 Received: by wizk4 with SMTP id k4so152029023wiz.1 for ; Tue, 05 May 2015 02:13:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-type:content-transfer-encoding; bh=HhQXKY07ie/9805deGhZq6H5Ww/NEip+ZWVd1CjH0MY=; b=Jf6lOcWlOBJsooBphkWsuUZCr+g0eBytq6RPZ0JBMnSIZ+ssSEMWZXrAQqMhyxQpDg fb0HbQK1HM7v2v2STRjwtWahDVfizX6QYmfKLDYkE3UCjG099PnwxobyHdYOpmXFnOHU 3fLCVaWJsNRXfqatuVdtYtPe7vUXkxGEnMXJZ63gb7F36aXuqU65Hlc2FkI5a+fdbMWj +SzDtNE1WZAKsFGzOhpqctcMvsHwN73ClUstgnNzdE7Bv1znQsFXRGzxAhpJ8ITlBbKd rIHLEwtjswQfY/l16jbq+euutYhvPVuvoK4OJ219eb0RJp1smhokmlQgABYpSkP01Psa Qpaw== X-Gm-Message-State: ALoCoQmYOe2Ds6oxX5phEwcgh41/nsmlmKLdtC1Ye5jGkmUJ5vgGZQfRWg0CvFCN7diT6NuvZc8N X-Received: by 10.180.74.104 with SMTP id s8mr2194487wiv.40.1430817223554; Tue, 05 May 2015 02:13:43 -0700 (PDT) Received: from jeremy-UX32VD.home (LPuteaux-656-1-278-113.w80-15.abo.wanadoo.fr. [80.15.154.113]) by mx.google.com with ESMTPSA id 16sm24523086wjs.41.2015.05.05.02.13.42 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 05 May 2015 02:13:42 -0700 (PDT) From: =?UTF-8?q?J=C3=A9r=C3=A9my=20Fangu=C3=A8de?= To: kvmarm@lists.cs.columbia.edu Date: Tue, 5 May 2015 11:13:11 +0200 Message-Id: <1430817191-6231-1-git-send-email-j.fanguede@virtualopensystems.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.212.176 Cc: kvm@vger.kernel.org, qemu-devel@nongnu.org, Christoffer Dall , Paolo Bonzini , =?UTF-8?q?J=C3=A9r=C3=A9my=20Fangu=C3=A8de?= , tech@virtualopensystems.com, linux-arm-kernel@lists.infradead.org Subject: [Qemu-devel] [RFC] ARM/ARM64: KVM: Implement KVM_FLUSH_DCACHE_GPA ioctl X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org To maintain cache coherency on ARM, we may need a mechanism to flush the data cache. This patch implements KVM_FLUSH_DCACHE_GPA vm ioctl which flushes the data cache at a specified address range. The input argument is a struct kvm_mem_addr containing the guest physical address and the length. Signed-off-by: Jérémy Fanguède --- arch/arm/kvm/arm.c | 13 +++++++++++++ include/uapi/linux/kvm.h | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index d9631ec..8638fd2 100644 --- a/arch/arm/kvm/arm.c +++ b/arch/arm/kvm/arm.c @@ -886,6 +886,19 @@ long kvm_arch_vm_ioctl(struct file *filp, return 0; } + case KVM_FLUSH_DCACHE_GPA: { + struct kvm_mem_addr mem_addr; + hva_t hva; + gpa_t gpa; + + if (copy_from_user(&mem_addr, argp, sizeof(mem_addr))) + return -EFAULT; + + gpa = mem_addr.addr; + hva = gfn_to_hva(kvm, gpa_to_gfn(gpa)) | (gpa & ~PAGE_MASK); + kvm_flush_dcache_to_poc((void *)hva, mem_addr.len); + return 0; + } default: return -EINVAL; } diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 4b60056..3bc599e 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -978,6 +978,11 @@ struct kvm_arm_device_addr { __u64 addr; }; +struct kvm_mem_addr { + __u64 addr; + __u32 len; +}; + /* * Device control API, available with KVM_CAP_DEVICE_CTRL */ @@ -1199,6 +1204,7 @@ struct kvm_s390_ucas_mapping { /* Available with KVM_CAP_S390_IRQ_STATE */ #define KVM_S390_SET_IRQ_STATE _IOW(KVMIO, 0xb5, struct kvm_s390_irq_state) #define KVM_S390_GET_IRQ_STATE _IOW(KVMIO, 0xb6, struct kvm_s390_irq_state) +#define KVM_FLUSH_DCACHE_GPA _IOW(KVMIO, 0xb7, struct kvm_mem_addr) #define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0) #define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1)