From patchwork Fri Apr 17 07:16:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 461942 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C47F81402C9 for ; Fri, 17 Apr 2015 17:17:35 +1000 (AEST) Received: from localhost ([::1]:39848 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yj0Wr-0007Qt-Hd for incoming@patchwork.ozlabs.org; Fri, 17 Apr 2015 03:17:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47200) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yj0WY-0006uv-3x for qemu-devel@nongnu.org; Fri, 17 Apr 2015 03:17:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yj0WU-00073h-VP for qemu-devel@nongnu.org; Fri, 17 Apr 2015 03:17:14 -0400 Received: from s16892447.onlinehome-server.info ([82.165.15.123]:57313) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yj0WU-00073G-Oj; Fri, 17 Apr 2015 03:17:10 -0400 Received: from 5d60c262.skybroadband.com ([93.96.194.98] helo=kentang.lan) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1Yj0WQ-0008CL-Ft; Fri, 17 Apr 2015 08:17:07 +0100 From: Mark Cave-Ayland To: stefanb@linux.vnet.ibm.com, agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org Date: Fri, 17 Apr 2015 08:16:49 +0100 Message-Id: <1429255009-12751-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 X-SA-Exim-Connect-IP: 93.96.194.98 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 82.165.15.123 Cc: Mark Cave-Ayland Subject: [Qemu-devel] [PATCH] target-ppc: don't invalidate msr MSR_HVB bit in cpu_post_load X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The invalidation code introduced in commit 2360b works by inverting most bits of env->msr to ensure that hreg_store_msr() will forcibly update the CPU env state to reflect the new msr value post-migration. Unfortunately hreg_store_msr() is called with alter_hv set to 0 which preserves the MSR_HVB state from the CPU env which is now the opposite value to what it should be. Ensure that we don't invalidate the msr MSR_HVB bit during cpu_post_load so that the correct value is restored. This fixes suspend/resume for PPC64. Reported-by: Stefan Berger Signed-off-by: Mark Cave-Ayland Reviewed-by: Alexander Graf --- target-ppc/machine.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/machine.c b/target-ppc/machine.c index 3921012..d875211 100644 --- a/target-ppc/machine.c +++ b/target-ppc/machine.c @@ -192,9 +192,9 @@ static int cpu_post_load(void *opaque, int version_id) ppc_store_sdr1(env, env->spr[SPR_SDR1]); } - /* Mark msr bits except MSR_TGPR invalid before restoring */ + /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */ msr = env->msr; - env->msr ^= ~(1ULL << MSR_TGPR); + env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); hreg_compute_mem_idx(env);