From patchwork Fri Apr 17 04:48:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Wang X-Patchwork-Id: 461918 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B6EBA1402C2 for ; Fri, 17 Apr 2015 14:53:53 +1000 (AEST) Received: from localhost ([::1]:39460 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiyHn-0000WV-Ic for incoming@patchwork.ozlabs.org; Fri, 17 Apr 2015 00:53:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47509) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiyDZ-0000cf-40 for qemu-devel@nongnu.org; Fri, 17 Apr 2015 00:49:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YiyDW-0006Oc-EL for qemu-devel@nongnu.org; Fri, 17 Apr 2015 00:49:29 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49631) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiyDW-0006OX-7z for qemu-devel@nongnu.org; Fri, 17 Apr 2015 00:49:26 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id t3H4nObM000615 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 17 Apr 2015 00:49:25 -0400 Received: from jason-ThinkPad-T430s.redhat.com (dhcp-14-122.nay.redhat.com [10.66.14.122]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t3H4mgm0017507; Fri, 17 Apr 2015 00:49:22 -0400 From: Jason Wang To: qemu-devel@nongnu.org Date: Fri, 17 Apr 2015 12:48:40 +0800 Message-Id: <1429246120-29439-17-git-send-email-jasowang@redhat.com> In-Reply-To: <1429246120-29439-1-git-send-email-jasowang@redhat.com> References: <1429246120-29439-1-git-send-email-jasowang@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: Keith Busch , Kevin Wolf , Jason Wang , Stefan Hajnoczi , mst@redhat.com Subject: [Qemu-devel] [PATCH v6 16/16] pci: remove hard-coded bar size in msix_init_exclusive_bar() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch lets msix_init_exclusive_bar() can calculate the bar and pba size based on the number of MSI-X vectors other than using a hard-coded limit 4096. This is needed to allow device to have more than 128 MSI_X vectors. To keep migration compatibility, keep using 4096 as bar size and 2048 for pba offset. Notes: We don't care about the case that using vectors > 128 for legacy machine type. Since we limit the queue max to 64, so vectors >= 65 is meaningless. Virtio device will be the first user for this. Cc: Keith Busch Cc: Kevin Wolf Cc: Stefan Hajnoczi Cc: Michael S. Tsirkin Signed-off-by: Jason Wang --- hw/pci/msix.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/hw/pci/msix.c b/hw/pci/msix.c index 24de260..f8748cf 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -295,29 +295,37 @@ int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries, { int ret; char *name; + uint32_t bar_size = 4096; + uint32_t bar_pba_offset = bar_size / 2; + uint32_t bar_pba_size = (nentries / 8 + 1) * 8; /* * Migration compatibility dictates that this remains a 4k * BAR with the vector table in the lower half and PBA in - * the upper half. Do not use these elsewhere! + * the upper half for nentries which is lower or equal to 128. + * No need to care about using more than 65 entries for legacy + * machine types who has at most 64 queues. */ -#define MSIX_EXCLUSIVE_BAR_SIZE 4096 -#define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0 -#define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2) -#define MSIX_EXCLUSIVE_CAP_OFFSET 0 + if (nentries * PCI_MSIX_ENTRY_SIZE > bar_pba_offset) { + bar_pba_offset = nentries * PCI_MSIX_ENTRY_SIZE; + } - if (nentries * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) { - return -EINVAL; + if (bar_pba_offset + bar_pba_size > 4096) { + bar_size = bar_pba_offset + bar_pba_size; + } + + if (bar_size & (bar_size - 1)) { + bar_size = 1 << qemu_fls(bar_size); } name = g_strdup_printf("%s-msix", dev->name); - memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, MSIX_EXCLUSIVE_BAR_SIZE); + memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), name, bar_size); g_free(name); ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr, - MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &dev->msix_exclusive_bar, - bar_nr, MSIX_EXCLUSIVE_BAR_PBA_OFFSET, - MSIX_EXCLUSIVE_CAP_OFFSET); + 0, &dev->msix_exclusive_bar, + bar_nr, bar_pba_offset, + 0); if (ret) { return ret; }