| Message ID | 1429113742-8371-6-git-send-email-greg.bellows@linaro.org |
|---|---|
| State | New |
| Headers | show |
On Wed, Apr 15, 2015 at 11:02:11AM -0500, Greg Bellows wrote: > From: Fabian Aggeler <aggelerf@ethz.ch> > > Security Extensions for GICv1 and GICv2 use register banking > to provide transparent access to seperate Secure and Non-secure > copies of GIC configuration registers. This function will later > be replaced by code determining the security state of a read/write > access to a register. Hi, Can we rebase this on top of Peters memory attribute series to get the actual secure attribute? Cheers, Edgar > > Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> > Signed-off-by: Greg Bellows <greg.bellows@linaro.org> > --- > hw/intc/arm_gic.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index cdf7408..e0bce6e 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -45,6 +45,13 @@ static inline int gic_get_current_cpu(GICState *s) > return 0; > } > > +/* Security state of a read / write access */ > +static inline bool ns_access(void) > +{ > + /* TODO: use actual security state */ > + return true; > +} > + > /* TODO: Many places that call this routine could be optimized. */ > /* Update interrupt status after enabled or pending bits have been changed. */ > void gic_update(GICState *s) > -- > 1.8.3.2 > >
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index cdf7408..e0bce6e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -45,6 +45,13 @@ static inline int gic_get_current_cpu(GICState *s) return 0; } +/* Security state of a read / write access */ +static inline bool ns_access(void) +{ + /* TODO: use actual security state */ + return true; +} + /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed. */ void gic_update(GICState *s)