From patchwork Wed Apr 15 16:02:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 461583 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4A5D2140134 for ; Thu, 16 Apr 2015 02:08:09 +1000 (AEST) Received: from localhost ([::1]:32982 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPrC-0001x6-DG for incoming@patchwork.ozlabs.org; Wed, 15 Apr 2015 12:08:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52163) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPmM-0002A7-4r for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YiPmJ-0001vd-B1 for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:06 -0400 Received: from mail-ob0-f179.google.com ([209.85.214.179]:33683) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YiPmJ-0001vS-7A for qemu-devel@nongnu.org; Wed, 15 Apr 2015 12:03:03 -0400 Received: by oblw8 with SMTP id w8so26503776obl.0 for ; Wed, 15 Apr 2015 09:03:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CbDxqZTh/6+j3cEO+Yie4BK0t62zKdlI2s7dpXUmTr0=; b=YF+n+qHWazaSZREvUuDmDMsu5c7h+yqOWhP2wrh3u0TBOElCwMnXw1Oi376hmgoUsY 8gB743nfNuVMxcOBgWvmYRki2qSe24Jdt4U2pkYCcmDaEnMCIi2kH24YH2XGEWx4HCgD ueSxe0BJbAtHoth5JwBatdaZ5JmnpZsUqON8k84dXyaxbA37hMKbCgE++psL19avzHMC OuXuZkQ26maJ3ZkTwtSUW49pJSW9wfo69WZAcAZwe4dw3xB1ODMtFsYFiZByOp2lZp2I zjkCzp5Xt0Gw5e19jNkXk6abwSVDvcK7Aa7oJ+R4QvtG83UX9FbvzpwfINUSEWNT2Qhe HhgQ== X-Gm-Message-State: ALoCoQlDpJPpgVwy+bzs8TYphAFkx1fbiJWVMeT1vEVcoWLC5rGD2Mun8WFBySFs7tDMPmIz7jtG X-Received: by 10.202.185.84 with SMTP id j81mr12522526oif.49.1429113757309; Wed, 15 Apr 2015 09:02:37 -0700 (PDT) Received: from gbellows-linaro.gateway.pace.com (99-179-1-214.lightspeed.austtx.sbcglobal.net. [99.179.1.214]) by mx.google.com with ESMTPSA id x142sm2567707oie.19.2015.04.15.09.02.35 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 15 Apr 2015 09:02:36 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 15 Apr 2015 11:02:10 -0500 Message-Id: <1429113742-8371-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> References: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.179 Cc: Fabian Aggeler , Greg Bellows Subject: [Qemu-devel] [PATCH v3 04/16] hw/intc/arm_gic: Add Security Extensions property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler The existing implementation does not support Security Extensions mentioned in the GICv1 and GICv2 architecture specification. Security Extensions are not available on all GICs. This property makes it possible to enable Security Extensions. It also makes GICD_TYPER/ICDICTR.SecurityExtn RAO for GICs which implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- v1 -> v2 - Change GICState security extension property from a uint8 type to bool --- hw/intc/arm_gic.c | 5 ++++- hw/intc/arm_gic_common.c | 1 + include/hw/intc/arm_gic_common.h | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index e9fb8b9..cdf7408 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -298,7 +298,10 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) if (offset == 0) return s->enabled; if (offset == 4) - return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); + /* Interrupt Controller Type Register */ + return ((s->num_irq / 32) - 1) + | ((NUM_CPU(s) - 1) << 5) + | (s->security_extn << 10); if (offset < 0x08) return 0; if (offset >= 0x80) { diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 18b01ba..e35049d 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -149,6 +149,7 @@ static Property arm_gic_common_properties[] = { * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) */ DEFINE_PROP_UINT32("revision", GICState, revision, 1), + DEFINE_PROP_BOOL("security-extn", GICState, security_extn, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 01c6f24..7825134 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -105,6 +105,7 @@ typedef struct GICState { MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ uint32_t num_irq; uint32_t revision; + bool security_extn; int dev_fd; /* kvm device fd if backed by kvm vgic support */ } GICState;