From patchwork Fri Mar 27 19:10:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 455550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5C922140157 for ; Sat, 28 Mar 2015 06:12:44 +1100 (AEDT) Received: from localhost ([::1]:51414 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YbZgQ-0003EX-Ep for incoming@patchwork.ozlabs.org; Fri, 27 Mar 2015 15:12:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49846) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YbZfB-0001hv-EJ for qemu-devel@nongnu.org; Fri, 27 Mar 2015 15:11:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YbZev-00058z-4r for qemu-devel@nongnu.org; Fri, 27 Mar 2015 15:11:25 -0400 Received: from mail-ob0-f176.google.com ([209.85.214.176]:32777) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YbZeu-00057x-Vr for qemu-devel@nongnu.org; Fri, 27 Mar 2015 15:11:09 -0400 Received: by obvd1 with SMTP id d1so14732757obv.0 for ; Fri, 27 Mar 2015 12:11:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5KYQgQ/1drWfrA9EAgQvknP5rc8qkRmJuP8pgig5Wi8=; b=i5gxFMjp/dN4LGTu1tllV4yw7o+lJ2N0bOAIVhU84/MKqYotLjv/Dzpnyns9sBrp2A gLT+mmH+yq3j9lkEEwaLlqjnnq2/mtM+ntPwHTpQ0GHmCzmti1w4leL0s0VPeEeHV2Vn gd9FUaErssHLacSaII9MKVUzI0P4Oq/zlksNDK7sdjYc5bUu2EfOJR1M8HbVv59mWhVO O+FM2k+XleWpO31mOMAx9MTwyp0JKKMDEYc5mPeLaHhVwojsPw/xeb1iyQXUTs1hr7O5 17zOD29dyW+UUJJWcrEFNQ1VS4SnxIpTmxLMk6I15RC72UFKKN0JflKBjJfnt2LcVo7f vL7w== X-Gm-Message-State: ALoCoQlP5DkyVWjUTL6SQJ8tzaHpUruza0hFlslWHFJ6Ouh6PDNecSZpTH6jJXwnc//23z4dGgmf X-Received: by 10.182.60.197 with SMTP id j5mr17286006obr.85.1427483468576; Fri, 27 Mar 2015 12:11:08 -0700 (PDT) Received: from gbellows-linaro.bellowshome.netattlocal.net (99-179-1-128.lightspeed.austtx.sbcglobal.net. [99.179.1.128]) by mx.google.com with ESMTPSA id hc7sm1490859obb.16.2015.03.27.12.11.06 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 27 Mar 2015 12:11:07 -0700 (PDT) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Fri, 27 Mar 2015 14:10:43 -0500 Message-Id: <1427483446-31900-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1427483446-31900-1-git-send-email-greg.bellows@linaro.org> References: <1427483446-31900-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.176 Cc: Greg Bellows Subject: [Qemu-devel] [[PATCH] 4/7] target-arm: Add AArch64 CPTR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows --- target-arm/cpu.h | 18 +++++++++++++++++- target-arm/helper.c | 43 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 59 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2178a1f..a811369 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -202,6 +202,7 @@ typedef struct CPUARMState { uint64_t sctlr_el[4]; }; uint64_t c1_coproc; /* Coprocessor access register. */ + uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ @@ -575,6 +576,10 @@ void pmccntr_sync(CPUARMState *env); #define SCTLR_AFE (1U << 29) #define SCTLR_TE (1U << 30) +#define CPTR_TCPAC (1U << 31) +#define CPTR_TTA (1U << 20) +#define CPTR_TFP (1U << 10) + #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) @@ -1813,9 +1818,20 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, int *flags) { int fpen; + int cur_el = arm_current_el(env); if (arm_feature(env, ARM_FEATURE_V6)) { - fpen = extract32(env->cp15.c1_coproc, 20, 2); + /* In AArch64, FP can be enabled differently depending on our EL. + * If our EL is 2 or 3, we use the EL specific CPTR to determine if FP + * is enabled. Otherwise, we fall back to using CPACR. + * CPTR.TFP is clear if FP is enabled whereas CPACR.FPEN is set to some + * degree. + */ + if (is_a64(env) && cur_el >= 2) { + fpen = !extract32(env->cp15.cptr_el[cur_el], 10, 1); + } else { + fpen = extract32(env->cp15.c1_coproc, 20, 2); + } } else { /* CPACR doesn't exist before v6, so VFP is always accessible */ fpen = 3; diff --git a/target-arm/helper.c b/target-arm/helper.c index 95383d5..00b457a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -592,6 +592,39 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, env->cp15.c1_coproc = value; } +static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri) +{ + int cur_el = arm_current_el(env); + bool secure = arm_is_secure(env); + + switch (ri->opc1) { + case 0: /* CPACR and CPACR_EL1 */ + if (arm_feature(env, ARM_FEATURE_V8) && cur_el == 1) { + /* Make sure we have EL2 before routine there */ + if (arm_feature(env, ARM_FEATURE_EL2) && !secure && + (env->cp15.cptr_el[2] & CPTR_TCPAC)) { + env->exception.target_el = 2; + return CP_ACCESS_TRAP; + /* Make sure we have EL3 before routine there */ + } else if (arm_feature(env, ARM_FEATURE_EL3) && + env->cp15.cptr_el[3] & CPTR_TCPAC) { + env->exception.target_el = 3; + return CP_ACCESS_TRAP; + } + } + break; + case 4: /* CPTR_EL2 */ + /* It is safe to assume we have EL2 and ARMv8 if we get here */ + if (cur_el == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) { + env->exception.target_el = 3; + return CP_ACCESS_TRAP; + } + break; + } + + return CP_ACCESS_OK; +} + static const ARMCPRegInfo v6_cp_reginfo[] = { /* prefetch by MVA in v6, NOP in v7 */ { .name = "MVA_prefetch", @@ -614,7 +647,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, - .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, + .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cptr_access, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc), .resetvalue = 0, .writefn = cpacr_write }, REGINFO_SENTINEL @@ -2537,6 +2570,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, .access = PL3_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, + { .name = "CPTR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, + .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) }, REGINFO_SENTINEL }; @@ -2598,6 +2635,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .access = PL3_RW, .writefn = vbar_write, .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]), .resetvalue = 0 }, + { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2, + .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) }, REGINFO_SENTINEL };