From patchwork Mon Mar 2 23:01:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 445465 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 83D161400D5 for ; Tue, 3 Mar 2015 10:04:31 +1100 (AEDT) Received: from localhost ([::1]:60280 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YSZO1-0003sT-Er for incoming@patchwork.ozlabs.org; Mon, 02 Mar 2015 18:04:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51460) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YSZLb-0007A9-6u for qemu-devel@nongnu.org; Mon, 02 Mar 2015 18:02:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YSZLW-00063g-K1 for qemu-devel@nongnu.org; Mon, 02 Mar 2015 18:01:59 -0500 Received: from s16892447.onlinehome-server.info ([82.165.15.123]:53727) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YSZLW-00063S-BW for qemu-devel@nongnu.org; Mon, 02 Mar 2015 18:01:54 -0500 Received: from 5d60c2ed.skybroadband.com ([93.96.194.237] helo=kentang.lan) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1YSZLS-0002p4-Hm; Mon, 02 Mar 2015 23:01:52 +0000 From: Mark Cave-Ayland To: qemu-devel@nongnu.org Date: Mon, 2 Mar 2015 23:01:14 +0000 Message-Id: <1425337280-21997-4-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1425337280-21997-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1425337280-21997-1-git-send-email-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 93.96.194.237 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 82.165.15.123 Cc: Mark Cave-Ayland , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH 3/9] m48t59: add a Nvram interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Hervé Poussineau Signed-off-by: Hervé Poussineau CC: Andreas Färber Signed-off-by: Mark Cave-Ayland --- hw/timer/m48t59.c | 59 +++++++++++++++++++++++++++++++++++++++++++++ include/hw/timer/m48t59.h | 24 ++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c index c46b63c..c5e74ce 100644 --- a/hw/timer/m48t59.c +++ b/hw/timer/m48t59.c @@ -798,6 +798,24 @@ static int m48t59_init1(SysBusDevice *dev) return 0; } +static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr) +{ + M48txxISAState *d = M48TXX_ISA(obj); + return m48t59_read(&d->state, addr); +} + +static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val) +{ + M48txxISAState *d = M48TXX_ISA(obj); + m48t59_write(&d->state, addr, val); +} + +static void m48txx_isa_toggle_lock(Nvram *obj, int lock) +{ + M48txxISAState *d = M48TXX_ISA(obj); + m48t59_toggle_lock(&d->state, lock); +} + static Property m48t59_isa_properties[] = { DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74), DEFINE_PROP_END_OF_LIST(), @@ -806,10 +824,14 @@ static Property m48t59_isa_properties[] = { static void m48txx_isa_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + NvramClass *nc = NVRAM_CLASS(klass); dc->realize = m48t59_isa_realize; dc->reset = m48t59_reset_isa; dc->props = m48t59_isa_properties; + nc->read = m48txx_isa_read; + nc->write = m48txx_isa_write; + nc->toggle_lock = m48txx_isa_toggle_lock; } static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data) @@ -820,13 +842,35 @@ static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data) u->info = *info; } +static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr) +{ + M48txxSysBusState *d = M48TXX_SYS_BUS(obj); + return m48t59_read(&d->state, addr); +} + +static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val) +{ + M48txxSysBusState *d = M48TXX_SYS_BUS(obj); + m48t59_write(&d->state, addr, val); +} + +static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock) +{ + M48txxSysBusState *d = M48TXX_SYS_BUS(obj); + m48t59_toggle_lock(&d->state, lock); +} + static void m48txx_sysbus_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + NvramClass *nc = NVRAM_CLASS(klass); k->init = m48t59_init1; dc->reset = m48t59_reset_sysbus; + nc->read = m48txx_sysbus_read; + nc->write = m48txx_sysbus_write; + nc->toggle_lock = m48txx_sysbus_toggle_lock; } static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data) @@ -837,12 +881,22 @@ static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data) u->info = *info; } +static const TypeInfo nvram_info = { + .name = TYPE_NVRAM, + .parent = TYPE_INTERFACE, + .class_size = sizeof(NvramClass), +}; + static const TypeInfo m48txx_sysbus_type_info = { .name = TYPE_M48TXX_SYS_BUS, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(M48txxSysBusState), .abstract = true, .class_init = m48txx_sysbus_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_NVRAM }, + { } + } }; static const TypeInfo m48txx_isa_type_info = { @@ -851,6 +905,10 @@ static const TypeInfo m48txx_isa_type_info = { .instance_size = sizeof(M48txxISAState), .abstract = true, .class_init = m48txx_isa_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_NVRAM }, + { } + } }; static void m48t59_register_types(void) @@ -867,6 +925,7 @@ static void m48t59_register_types(void) }; int i; + type_register_static(&nvram_info); type_register_static(&m48txx_sysbus_type_info); type_register_static(&m48txx_isa_type_info); diff --git a/include/hw/timer/m48t59.h b/include/hw/timer/m48t59.h index 8217522..ddbbda2 100644 --- a/include/hw/timer/m48t59.h +++ b/include/hw/timer/m48t59.h @@ -1,6 +1,9 @@ #ifndef NVRAM_H #define NVRAM_H +#include "qemu-common.h" +#include "qom/object.h" + /* NVRAM helpers */ typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr); typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val); @@ -34,4 +37,25 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, uint32_t io_base, uint16_t size, int type); +#define TYPE_NVRAM "nvram" + +#define NVRAM_CLASS(klass) \ + OBJECT_CLASS_CHECK(NvramClass, (klass), TYPE_NVRAM) +#define NVRAM_GET_CLASS(obj) \ + OBJECT_GET_CLASS(NvramClass, (obj), TYPE_NVRAM) +#define NVRAM(obj) \ + INTERFACE_CHECK(Nvram, (obj), TYPE_NVRAM) + +typedef struct Nvram { + Object parent; +} Nvram; + +typedef struct NvramClass { + InterfaceClass parent; + + uint32_t (*read)(Nvram *obj, uint32_t addr); + void (*write)(Nvram *obj, uint32_t addr, uint32_t val); + void (*toggle_lock)(Nvram *obj, int lock); +} NvramClass; + #endif /* !NVRAM_H */