From patchwork Thu Feb 12 10:29:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 439151 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6C7C414017B for ; Thu, 12 Feb 2015 21:31:50 +1100 (AEDT) Received: from localhost ([::1]:49472 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLr3k-0003QZ-Hs for incoming@patchwork.ozlabs.org; Thu, 12 Feb 2015 05:31:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48324) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLr20-0000Qj-Ja for qemu-devel@nongnu.org; Thu, 12 Feb 2015 05:30:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YLr1t-0007IX-Qq for qemu-devel@nongnu.org; Thu, 12 Feb 2015 05:30:00 -0500 Received: from mail-ie0-f174.google.com ([209.85.223.174]:36909) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLr1t-0007IS-IX for qemu-devel@nongnu.org; Thu, 12 Feb 2015 05:29:53 -0500 Received: by iecrl12 with SMTP id rl12so8386047iec.4 for ; Thu, 12 Feb 2015 02:29:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZyQOaLMoxILJXWGLPUu+zoAgr+Itw08KwW6rOaUp14M=; b=OQcVourcSM4WvF6gryCb8z9qbwsgC6hU8Adnng0d3HTkD59mWGH815WxrUoynqV+lg 1elKNhj7o3KWYn2B8d79XZzDiQ/0+NMrnVu4tHA44WtIHYbkp2ui7PlqSkkCvnNO3cae UFdT7yPwto4+F8x9UXZ7euu9LlzDVGg96XJ7Po7hZN/osnoa0q1gpP9QTVI6RBdMiclT hOU7I/QMxWZQWgBrxQw7sHyF0X0iGjHQ/kreQAHZumE8hQSP8kb8mW7jDbV7c+bwexas iK4XjnQdstkv7K519bBKvt6MS89dQjZl3OpsEGLosKka+Xd6DGowSE037MOsbf4+4BA5 3XgA== X-Gm-Message-State: ALoCoQnrS8YIjMXZmPpFb0S6iJ06XPmKKN9qIo7kaE2ZZOrGXXN6H8XA+mQDcOaz+mro5gjogEQc X-Received: by 10.107.15.96 with SMTP id x93mr3319004ioi.75.1423736993167; Thu, 12 Feb 2015 02:29:53 -0800 (PST) Received: from localhost.localdomain ([113.28.134.59]) by mx.google.com with ESMTPSA id p138sm2177027ioe.9.2015.02.12.02.29.50 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 12 Feb 2015 02:29:52 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, christoffer.dall@linaro.org, alex.bennee@linaro.org Date: Thu, 12 Feb 2015 18:29:31 +0800 Message-Id: <1423736974-14254-2-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1423736974-14254-1-git-send-email-greg.bellows@linaro.org> References: <1423736974-14254-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.223.174 Cc: edgar.iglesias@gmail.com, Greg Bellows , a.spyridakis@virtualopensystems.com Subject: [Qemu-devel] [PATCH v8 1/4] target-arm: Add CPU property to disable AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Adds registration and get/set functions for enabling/disabling the AArch64 execution state on AArch64 CPUs. By default AArch64 execution state is enabled on AArch64 CPUs, setting the property to off, will disable the execution state. The below QEMU invocation would have AArch64 execution state disabled. $ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off Also adds stripping of features from CPU model string in acquiring the ARM CPU by name. Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v4 -> v5 - Fix error message. v3 -> v4 - Switch from using strtok to g_strsplit - Add disablement of aarch64 option if KVM is not enabled. v1 -> v2 - Scrap the custom CPU feature parsing in favor of using the default CPU parsing. - Add registration of CPU AArch64 property to disable/enable the AArch64 feature. --- target-arm/cpu.c | 5 ++++- target-arm/cpu64.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index d38af74..986f04c 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -544,13 +544,16 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; char *typename; + char **cpuname; if (!cpu_model) { return NULL; } - typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model); + cpuname = g_strsplit(cpu_model, ",", 1); + typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); oc = object_class_by_name(typename); + g_strfreev(cpuname); g_free(typename); if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || object_class_is_abstract(oc)) { diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index bb778b3..823c739 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -32,6 +32,11 @@ static inline void set_feature(CPUARMState *env, int feature) env->features |= 1ULL << feature; } +static inline void unset_feature(CPUARMState *env, int feature) +{ + env->features &= ~(1ULL << feature); +} + #ifndef CONFIG_USER_ONLY static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -170,8 +175,42 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = NULL } }; +static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); +} + +static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + /* At this time, this property is only allowed if KVM is enabled. This + * restriction allows us to avoid fixing up functionality that assumes a + * uniform execution state like do_interrupt. + */ + if (!kvm_enabled()) { + error_setg(errp, "'aarch64' feature cannot be disabled " + "unless KVM is enabled"); + return; + } + + if (value == false) { + unset_feature(&cpu->env, ARM_FEATURE_AARCH64); + } else { + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + } +} + static void aarch64_cpu_initfn(Object *obj) { + object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, + aarch64_cpu_set_aarch64, NULL); + object_property_set_description(obj, "aarch64", + "Set on/off to enable/disable aarch64 " + "execution state ", + NULL); } static void aarch64_cpu_finalizefn(Object *obj)