From patchwork Thu Feb 12 02:59:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 438998 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9D29614011D for ; Thu, 12 Feb 2015 14:00:25 +1100 (AEDT) Received: from localhost ([::1]:47947 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLk0t-0006GX-TR for incoming@patchwork.ozlabs.org; Wed, 11 Feb 2015 22:00:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60018) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLk0F-0005Bo-PW for qemu-devel@nongnu.org; Wed, 11 Feb 2015 21:59:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YLk0A-0007eW-Jv for qemu-devel@nongnu.org; Wed, 11 Feb 2015 21:59:43 -0500 Received: from mail-pd0-f173.google.com ([209.85.192.173]:37496) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YLk0A-0007eN-Eg for qemu-devel@nongnu.org; Wed, 11 Feb 2015 21:59:38 -0500 Received: by pdbfl12 with SMTP id fl12so8750127pdb.4 for ; Wed, 11 Feb 2015 18:59:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W1f33DfFnuZ+1vxkjRwBmQCALIWbBwrNDBSjMwYZnIw=; b=KgJwDtXzRYJq8YDF2UPaRRM4Api0i0QVP6M978R4M30ChNbaVvMS+ISLtJHbcKhUkt bbM6sYQg2p3ZH6p68t99h0N/BaVFQBvb/3dbnp6g6i9eF0fJKWM9T3KJQNN4KTKC7BrT mCmDxdDwj9v8wRZ/qDcGkaaWasanYLvp6+Lzxz070HuILI1ybobO005voxITzV154KRN PzQ+Wzgd9kVdgAA7GtcqKjfo2fJb93TzWSU9yMvLfP7nqBeHcsxBmKNaF3S0L6wkA8Er EQI4yOyN8XwQ2Gm052hwDWLq+UW+5kvbr015R6ThwX9eQDw3MYP9d0wYZjkieUzQcarW JSVQ== X-Gm-Message-State: ALoCoQmf/4giXfKidsPGE6sb1MGUoFduBhKWLFCZM3I83w+BVHduFkJUaKyLdFdAh0BqZjydUAJ3 X-Received: by 10.70.44.66 with SMTP id c2mr2620765pdm.51.1423709977728; Wed, 11 Feb 2015 18:59:37 -0800 (PST) Received: from localhost.localdomain ([210.177.145.249]) by mx.google.com with ESMTPSA id fy8sm2140272pdb.42.2015.02.11.18.59.35 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 11 Feb 2015 18:59:37 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, christoffer.dall@linaro.org, alex.bennee@linaro.org Date: Thu, 12 Feb 2015 10:59:05 +0800 Message-Id: <1423709948-7662-2-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1423709948-7662-1-git-send-email-greg.bellows@linaro.org> References: <1423709948-7662-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.173 Cc: edgar.iglesias@gmail.com, Greg Bellows , a.spyridakis@virtualopensystems.com Subject: [Qemu-devel] [PATCH v5 1/4] target-arm: Add CPU property to disable AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Adds registration and get/set functions for enabling/disabling the AArch64 execution state on AArch64 CPUs. By default AArch64 execution state is enabled on AArch64 CPUs, setting the property to off, will disable the execution state. The below QEMU invocation would have AArch64 execution state disabled. $ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off Also adds stripping of features from CPU model string in acquiring the ARM CPU by name. Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v4 -> v5 - Fix error message. v3 -> v4 - Switch from using strtok to g_strsplit - Add disablement of aarch64 option if KVM is not enabled. v1 -> v2 - Scrap the custom CPU feature parsing in favor of using the default CPU parsing. - Add registration of CPU AArch64 property to disable/enable the AArch64 feature. --- target-arm/cpu.c | 5 ++++- target-arm/cpu64.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index d38af74..986f04c 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -544,13 +544,16 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; char *typename; + char **cpuname; if (!cpu_model) { return NULL; } - typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model); + cpuname = g_strsplit(cpu_model, ",", 1); + typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]); oc = object_class_by_name(typename); + g_strfreev(cpuname); g_free(typename); if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || object_class_is_abstract(oc)) { diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index bb778b3..823c739 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -32,6 +32,11 @@ static inline void set_feature(CPUARMState *env, int feature) env->features |= 1ULL << feature; } +static inline void unset_feature(CPUARMState *env, int feature) +{ + env->features &= ~(1ULL << feature); +} + #ifndef CONFIG_USER_ONLY static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -170,8 +175,42 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = NULL } }; +static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); +} + +static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + /* At this time, this property is only allowed if KVM is enabled. This + * restriction allows us to avoid fixing up functionality that assumes a + * uniform execution state like do_interrupt. + */ + if (!kvm_enabled()) { + error_setg(errp, "'aarch64' feature cannot be disabled " + "unless KVM is enabled"); + return; + } + + if (value == false) { + unset_feature(&cpu->env, ARM_FEATURE_AARCH64); + } else { + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + } +} + static void aarch64_cpu_initfn(Object *obj) { + object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, + aarch64_cpu_set_aarch64, NULL); + object_property_set_description(obj, "aarch64", + "Set on/off to enable/disable aarch64 " + "execution state ", + NULL); } static void aarch64_cpu_finalizefn(Object *obj)