From patchwork Tue Jan 27 23:58:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 433726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B9CFC140284 for ; Wed, 28 Jan 2015 10:59:37 +1100 (AEDT) Received: from localhost ([::1]:50580 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGG2h-00087W-OX for incoming@patchwork.ozlabs.org; Tue, 27 Jan 2015 18:59:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35317) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGG25-0006s9-Fx for qemu-devel@nongnu.org; Tue, 27 Jan 2015 18:59:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YGG22-0005Uh-6N for qemu-devel@nongnu.org; Tue, 27 Jan 2015 18:58:57 -0500 Received: from mail-pa0-f43.google.com ([209.85.220.43]:49494) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGG22-0005UX-1w for qemu-devel@nongnu.org; Tue, 27 Jan 2015 18:58:54 -0500 Received: by mail-pa0-f43.google.com with SMTP id eu11so21661214pac.2 for ; Tue, 27 Jan 2015 15:58:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1GXtsvznQsofArJhvx1iMPA1oMWGmi5zbWjEYn/pMoc=; b=ULhZho0TZiR7nK7W+x4AuIFFdjBq43GOqgvGO5T5CflY+SYFbVV1awrbU+lWsVa/w/ hXS19vxaFpSZChwNcvwtrMTSe7jhtasvtXvshdOkAWAacUjxS5feqrKWv1AxaTieY7Ee 7CLIfbOiKQrLM7eufXBQdmMyaj1iDH+vEIwiT3wKouxlYPKIcFWbEW3yj6b1NUHWaji4 AthvxFkX/aWsVIrH4mtggAv4CZjdCijSvPTGHEg4dnd0x6xw40dPLLoTMP/nwmDHSMbB pu9UtUt5c9qEYVtfhsLoTnUUUTS8ZcuHubsVRY3uEvMZLvTJdVLLH3YK/jCKRF+JVh76 Fs0w== X-Gm-Message-State: ALoCoQnNElPNyW5YXE/mzExGZ9QnnJ2a8Vc7BICoGSKiy65Q0AHcrsQADYwhnqCwagcmOCvcN5uM X-Received: by 10.66.160.66 with SMTP id xi2mr185357pab.3.1422403133345; Tue, 27 Jan 2015 15:58:53 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id nu5sm2679909pbb.79.2015.01.27.15.58.51 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 27 Jan 2015 15:58:52 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, christoffer.dall@linaro.org, alex.bennee@linaro.org Date: Tue, 27 Jan 2015 17:58:37 -0600 Message-Id: <1422403117-16921-5-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1422403117-16921-1-git-send-email-greg.bellows@linaro.org> References: <1422403117-16921-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.43 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v3 4/4] target-arm: Add AArch32 guest support to KVM64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add 32-bit to/from 64-bit register synchronization on register gets and puts. Set EL1_32BIT feature flag passed to KVM Signed-off-by: Greg Bellows --- v2 -> v3 - Conditionalize sync of 32-bit and 64-bit registers --- target-arm/kvm64.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index ba16821..924b423 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -81,8 +81,7 @@ int kvm_arch_init_vcpu(CPUState *cs) int ret; ARMCPU *cpu = ARM_CPU(cs); - if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || - !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) { fprintf(stderr, "KVM is not supported for this guest CPU type\n"); return -EINVAL; } @@ -96,6 +95,9 @@ int kvm_arch_init_vcpu(CPUState *cs) cpu->psci_version = 2; cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2; } + if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT; + } /* Do KVM_ARM_VCPU_INIT ioctl */ ret = kvm_arm_vcpu_init(cs); @@ -133,6 +135,13 @@ int kvm_arch_put_registers(CPUState *cs, int level) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + /* If we are in AArch32 mode then we need to sync the AArch64 regs with the + * AArch32 regs before pushing them out 64-bit KVM. + */ + if (!is_a64(env)) { + aarch64_sync_32_to_64(env); + } + for (i = 0; i < 31; i++) { reg.id = AARCH64_CORE_REG(regs.regs[i]); reg.addr = (uintptr_t) &env->xregs[i]; @@ -162,7 +171,11 @@ int kvm_arch_put_registers(CPUState *cs, int level) } /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ - val = pstate_read(env); + if (is_a64(env)) { + val = pstate_read(env); + } else { + val = cpsr_read(env); + } reg.id = AARCH64_CORE_REG(regs.pstate); reg.addr = (uintptr_t) &val; ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); @@ -219,6 +232,13 @@ int kvm_arch_get_registers(CPUState *cs) } } + /* If we are in AArch32 mode then we need to sync the AArch32 regs with the + * incoming AArch64 regs received from 64-bit KVM. + */ + if (!is_a64(env)) { + aarch64_sync_64_to_32(env); + } + reg.id = AARCH64_CORE_REG(regs.sp); reg.addr = (uintptr_t) &env->sp_el[0]; ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); @@ -239,7 +259,12 @@ int kvm_arch_get_registers(CPUState *cs) if (ret) { return ret; } - pstate_write(env, val); + if (is_a64(env)) { + pstate_write(env, val); + } else { + env->uncached_cpsr = val & CPSR_M; + cpsr_write(env, val, 0xffffffff); + } /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the * QEMU side we keep the current SP in xregs[31] as well.