| Message ID | 1422091280-14532-11-git-send-email-zhaoshenglong@huawei.com |
|---|---|
| State | New |
| Headers | show |
On Sat, 24 Jan 2015 17:21:19 +0800 Shannon Zhao <zhaoshenglong@huawei.com> wrote: > DSDT consists of the usual common table header plus a definition > block in AML encoding which describes all devices in the platform. > > After initializing DSDT with header information the namespace is > created which is followed by the device encodings. The devices are > described using the Resource Template for the 32-Bit Fixed Memory > Range and the Extended Interrupt Descriptors. > > The following devices are included in the DSDT: > - CPUs > - UART > - RTC > - NAND Flash > - virtio-mmio > > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> > --- > hw/arm/virt-acpi-build.c | 120 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 files changed, 120 insertions(+), 0 deletions(-) > > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c > index de1f307..5c76ca2 100644 > --- a/hw/arm/virt-acpi-build.c > +++ b/hw/arm/virt-acpi-build.c > @@ -98,6 +98,111 @@ static inline void acpi_add_table(GArray *table_offsets, GArray *table_data) > g_array_append_val(table_offsets, offset); > } > > +static void acpi_dsdt_add_cpus(AcpiAml *scope, int smp_cpus) > +{ > + AcpiAml dev, crs; > + int i; > + char name[5]; > + for (i = 0; i < smp_cpus; i++) { I'm not sure about ARM butm shouldn't not present but possble CPUs also described here? PS: One more thing about CPU hotplug, I'd like current (x86) bitmap based QEMU<->APCI interface (which scales only upto 256 CPU) have redone to a one similar to memory hotplug first. So that ARM wouldn't have to support compatibility mode for it in the future. > + snprintf(name, 5, "CPU%u", i); > + dev = acpi_device("%s", name); > + aml_append(&dev, acpi_name_decl("_HID", acpi_string("ACPI007"))); > + aml_append(&dev, acpi_name_decl("_UID", acpi_int(i))); > + crs = acpi_resource_template(); > + aml_append(&dev, acpi_name_decl("_CRS", crs)); > + aml_append(scope, dev); > + } > +} > + > +static void acpi_dsdt_add_uart(AcpiAml *scope, const hwaddr *uart_addr, > + const int *uart_irq) > +{ > + AcpiAml dev, crs; > + > + dev = acpi_device("COM0"); > + aml_append(&dev, acpi_name_decl("_HID", acpi_string("ARMH0011"))); > + aml_append(&dev, acpi_name_decl("_UID", acpi_int(0))); > + > + crs = acpi_resource_template(); > + aml_append(&crs, > + acpi_fixed_memory32(uart_addr[0], uart_addr[1], 0x01)); > + aml_append(&crs, > + acpi_extended_irq(0x01, *uart_irq + 32)); > + aml_append(&dev, acpi_name_decl("_CRS", crs)); > + aml_append(scope, dev); > +} > + > +static void acpi_dsdt_add_rtc(AcpiAml *scope, const hwaddr *rtc_addr, > + const int *rtc_irq) > +{ > + AcpiAml dev, crs; > + > + dev = acpi_device("RTC0"); > + aml_append(&dev, acpi_name_decl("_HID", acpi_string("LNRO0013"))); > + aml_append(&dev, acpi_name_decl("_UID", acpi_int(0))); > + > + crs = acpi_resource_template(); > + aml_append(&crs, > + acpi_fixed_memory32(rtc_addr[0], rtc_addr[1], 0x01)); > + aml_append(&crs, > + acpi_extended_irq(0x01, *rtc_irq + 32)); > + aml_append(&dev, acpi_name_decl("_CRS", crs)); > + aml_append(scope, dev); > +} > + > +static void acpi_dsdt_add_flash(AcpiAml *scope, const hwaddr *flash_addr) > +{ > + AcpiAml dev, crs; > + hwaddr base = flash_addr[0]; > + hwaddr size = flash_addr[1]; > + > + dev = acpi_device("FLS0"); > + aml_append(&dev, acpi_name_decl("_HID", acpi_string("LNRO0015"))); > + aml_append(&dev, acpi_name_decl("_UID", acpi_int(0))); > + > + crs = acpi_resource_template(); > + aml_append(&crs, > + acpi_fixed_memory32(base, size, 0x01)); > + aml_append(&dev, acpi_name_decl("_CRS", crs)); > + aml_append(scope, dev); > + > + dev = acpi_device("FLS1"); > + aml_append(&dev, acpi_name_decl("_HID", acpi_string("LNRO0015"))); > + aml_append(&dev, acpi_name_decl("_UID", acpi_int(1))); > + crs = acpi_resource_template(); > + aml_append(&crs, > + acpi_fixed_memory32(base + size, size, 0x01)); > + aml_append(&dev, acpi_name_decl("_CRS", crs)); > + aml_append(scope, dev); > +} > + > +static void acpi_dsdt_add_virtio(AcpiAml *scope, const hwaddr *mmio_addrs, > + const int *mmio_irq, int num) > +{ > + AcpiAml dev, crs; > + hwaddr base = mmio_addrs[0]; > + hwaddr size = mmio_addrs[1]; > + int irq = *mmio_irq + 32; > + int i; > + char name[5]; > + > + for (i = 0; i < num; i++) { > + snprintf(name, 5, "VR%02u", i); > + dev = acpi_device("%s", name); > + aml_append(&dev, acpi_name_decl("_HID", acpi_string("LNRO0005"))); > + aml_append(&dev, acpi_name_decl("_UID", acpi_int(i))); > + > + crs = acpi_resource_template(); > + aml_append(&crs, > + acpi_fixed_memory32(base, size, 0x01)); > + aml_append(&crs, > + acpi_extended_irq(0x01, irq + i)); > + aml_append(&dev, acpi_name_decl("_CRS", crs)); > + aml_append(scope, dev); > + base += size; > + } > +} > + > /* RSDP */ > static GArray * > build_rsdp(GArray *rsdp_table, GArray *linker, uint64_t xsdt) > @@ -260,6 +365,21 @@ build_facs(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) > static void > build_dsdt(AcpiAml *table_aml, GArray *linker, VirtGuestInfo *guest_info) > { > + AcpiAml scope, dsdt; > + const struct acpi_dsdt_info *info = guest_info->dsdt_info; > + > + dsdt = acpi_def_block("DSDT", 1, ACPI_VIRT_QEMU_STR_4, > + ACPI_VIRT_MACH_STR_8, 1); > + scope = acpi_scope("\\_SB"); > + acpi_dsdt_add_cpus(&scope, guest_info->nb_cpus); > + acpi_dsdt_add_uart(&scope, info->uart_addr, info->uart_irq); > + acpi_dsdt_add_rtc(&scope, info->rtc_addr, info->rtc_irq); > + acpi_dsdt_add_flash(&scope, info->flash_addr); > + acpi_dsdt_add_virtio(&scope, info->virtio_mmio_addr, > + info->virtio_mmio_irq, info->virtio_mmio_num); > + > + aml_append(&dsdt, scope); > + aml_append(table_aml, dsdt); > } > > typedef
On 2015/1/26 18:40, Igor Mammedov wrote: > On Sat, 24 Jan 2015 17:21:19 +0800 > Shannon Zhao <zhaoshenglong@huawei.com> wrote: > >> > DSDT consists of the usual common table header plus a definition >> > block in AML encoding which describes all devices in the platform. >> > >> > After initializing DSDT with header information the namespace is >> > created which is followed by the device encodings. The devices are >> > described using the Resource Template for the 32-Bit Fixed Memory >> > Range and the Extended Interrupt Descriptors. >> > >> > The following devices are included in the DSDT: >> > - CPUs >> > - UART >> > - RTC >> > - NAND Flash >> > - virtio-mmio >> > >> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> >> > --- >> > hw/arm/virt-acpi-build.c | 120 ++++++++++++++++++++++++++++++++++++++++++++++ >> > 1 files changed, 120 insertions(+), 0 deletions(-) >> > >> > diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c >> > index de1f307..5c76ca2 100644 >> > --- a/hw/arm/virt-acpi-build.c >> > +++ b/hw/arm/virt-acpi-build.c >> > @@ -98,6 +98,111 @@ static inline void acpi_add_table(GArray *table_offsets, GArray *table_data) >> > g_array_append_val(table_offsets, offset); >> > } >> > >> > +static void acpi_dsdt_add_cpus(AcpiAml *scope, int smp_cpus) >> > +{ >> > + AcpiAml dev, crs; >> > + int i; >> > + char name[5]; >> > + for (i = 0; i < smp_cpus; i++) { > I'm not sure about ARM butm shouldn't not present but possble CPUs > also described here? > In struct VirtGuestInfo there are nb_cpus and max_cpus. nb_cpus stands present CPUs while max_cpus stands possible CPUs. We can use them to create bitmap. > PS: > One more thing about CPU hotplug, I'd like current (x86) bitmap based > QEMU<->APCI interface (which scales only upto 256 CPU) have redone > to a one similar to memory hotplug first. > So that ARM wouldn't have to support compatibility mode for it in the future. > Good idea :-) Thanks, Shannon
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index de1f307..5c76ca2 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -98,6 +98,111 @@ static inline void acpi_add_table(GArray *table_offsets, GArray *table_data) g_array_append_val(table_offsets, offset); } +static void acpi_dsdt_add_cpus(AcpiAml *scope, int smp_cpus) +{ + AcpiAml dev, crs; + int i; + char name[5]; + for (i = 0; i < smp_cpus; i++) { + snprintf(name, 5, "CPU%u", i); + dev = acpi_device("%s", name); + aml_append(&dev, acpi_name_decl("_HID", acpi_string("ACPI007"))); + aml_append(&dev, acpi_name_decl("_UID", acpi_int(i))); + crs = acpi_resource_template(); + aml_append(&dev, acpi_name_decl("_CRS", crs)); + aml_append(scope, dev); + } +} + +static void acpi_dsdt_add_uart(AcpiAml *scope, const hwaddr *uart_addr, + const int *uart_irq) +{ + AcpiAml dev, crs; + + dev = acpi_device("COM0"); + aml_append(&dev, acpi_name_decl("_HID", acpi_string("ARMH0011"))); + aml_append(&dev, acpi_name_decl("_UID", acpi_int(0))); + + crs = acpi_resource_template(); + aml_append(&crs, + acpi_fixed_memory32(uart_addr[0], uart_addr[1], 0x01)); + aml_append(&crs, + acpi_extended_irq(0x01, *uart_irq + 32)); + aml_append(&dev, acpi_name_decl("_CRS", crs)); + aml_append(scope, dev); +} + +static void acpi_dsdt_add_rtc(AcpiAml *scope, const hwaddr *rtc_addr, + const int *rtc_irq) +{ + AcpiAml dev, crs; + + dev = acpi_device("RTC0"); + aml_append(&dev, acpi_name_decl("_HID", acpi_string("LNRO0013"))); + aml_append(&dev, acpi_name_decl("_UID", acpi_int(0))); + + crs = acpi_resource_template(); + aml_append(&crs, + acpi_fixed_memory32(rtc_addr[0], rtc_addr[1], 0x01)); + aml_append(&crs, + acpi_extended_irq(0x01, *rtc_irq + 32)); + aml_append(&dev, acpi_name_decl("_CRS", crs)); + aml_append(scope, dev); +} + +static void acpi_dsdt_add_flash(AcpiAml *scope, const hwaddr *flash_addr) +{ + AcpiAml dev, crs; + hwaddr base = flash_addr[0]; + hwaddr size = flash_addr[1]; + + dev = acpi_device("FLS0"); + aml_append(&dev, acpi_name_decl("_HID", acpi_string("LNRO0015"))); + aml_append(&dev, acpi_name_decl("_UID", acpi_int(0))); + + crs = acpi_resource_template(); + aml_append(&crs, + acpi_fixed_memory32(base, size, 0x01)); + aml_append(&dev, acpi_name_decl("_CRS", crs)); + aml_append(scope, dev); + + dev = acpi_device("FLS1"); + aml_append(&dev, acpi_name_decl("_HID", acpi_string("LNRO0015"))); + aml_append(&dev, acpi_name_decl("_UID", acpi_int(1))); + crs = acpi_resource_template(); + aml_append(&crs, + acpi_fixed_memory32(base + size, size, 0x01)); + aml_append(&dev, acpi_name_decl("_CRS", crs)); + aml_append(scope, dev); +} + +static void acpi_dsdt_add_virtio(AcpiAml *scope, const hwaddr *mmio_addrs, + const int *mmio_irq, int num) +{ + AcpiAml dev, crs; + hwaddr base = mmio_addrs[0]; + hwaddr size = mmio_addrs[1]; + int irq = *mmio_irq + 32; + int i; + char name[5]; + + for (i = 0; i < num; i++) { + snprintf(name, 5, "VR%02u", i); + dev = acpi_device("%s", name); + aml_append(&dev, acpi_name_decl("_HID", acpi_string("LNRO0005"))); + aml_append(&dev, acpi_name_decl("_UID", acpi_int(i))); + + crs = acpi_resource_template(); + aml_append(&crs, + acpi_fixed_memory32(base, size, 0x01)); + aml_append(&crs, + acpi_extended_irq(0x01, irq + i)); + aml_append(&dev, acpi_name_decl("_CRS", crs)); + aml_append(scope, dev); + base += size; + } +} + /* RSDP */ static GArray * build_rsdp(GArray *rsdp_table, GArray *linker, uint64_t xsdt) @@ -260,6 +365,21 @@ build_facs(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info) static void build_dsdt(AcpiAml *table_aml, GArray *linker, VirtGuestInfo *guest_info) { + AcpiAml scope, dsdt; + const struct acpi_dsdt_info *info = guest_info->dsdt_info; + + dsdt = acpi_def_block("DSDT", 1, ACPI_VIRT_QEMU_STR_4, + ACPI_VIRT_MACH_STR_8, 1); + scope = acpi_scope("\\_SB"); + acpi_dsdt_add_cpus(&scope, guest_info->nb_cpus); + acpi_dsdt_add_uart(&scope, info->uart_addr, info->uart_irq); + acpi_dsdt_add_rtc(&scope, info->rtc_addr, info->rtc_irq); + acpi_dsdt_add_flash(&scope, info->flash_addr); + acpi_dsdt_add_virtio(&scope, info->virtio_mmio_addr, + info->virtio_mmio_irq, info->virtio_mmio_num); + + aml_append(&dsdt, scope); + aml_append(table_aml, dsdt); } typedef
DSDT consists of the usual common table header plus a definition block in AML encoding which describes all devices in the platform. After initializing DSDT with header information the namespace is created which is followed by the device encodings. The devices are described using the Resource Template for the 32-Bit Fixed Memory Range and the Extended Interrupt Descriptors. The following devices are included in the DSDT: - CPUs - UART - RTC - NAND Flash - virtio-mmio Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> --- hw/arm/virt-acpi-build.c | 120 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 120 insertions(+), 0 deletions(-)