From patchwork Fri Jan 23 14:49:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 432185 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CF5921402E7 for ; Sat, 24 Jan 2015 01:50:19 +1100 (AEDT) Received: from localhost ([::1]:59527 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYw-0001Nf-3f for incoming@patchwork.ozlabs.org; Fri, 23 Jan 2015 09:50:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYM-0000HN-Ka for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YEfYI-0005H0-28 for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:42 -0500 Received: from mail-pd0-f182.google.com ([209.85.192.182]:62731) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YEfYH-0005Gs-TV for qemu-devel@nongnu.org; Fri, 23 Jan 2015 09:49:38 -0500 Received: by mail-pd0-f182.google.com with SMTP id z10so6545129pdj.13 for ; Fri, 23 Jan 2015 06:49:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A8FSkrtj2Ph3iZVn3xAj6nnionHWPBPdrLkFT/bAiQE=; b=byKErdEE2ZUYBhZZTo3HksBp08Pk+XEA9DKnddZS8FA0tchsl7lZbeQKzoD7dKsSQE GAeyIEW2Fdc/lotR8kqmEFmjVEvwFXuJnwUm9wiev2aFBc+aRXJDDUeskhsC1UYqmagK gr1qhDNmDfWTdBKTLc6tlbJqqthQAUn7knlluVoBvr56FLwcWC6uV/R6LgAI0rvPYHcq wJlxyjQIEgtP8fh86aue7cBfIBlvmJg6TbFzWdKt/R6IIN1LC2E6PIwS5VlWk3ZRjmkg xZQ0Bn+BAiPMxT6ezgg+WN1TjaTB25FA9bWILbmq6Vc0iD9+LURQOJrlpeZBZZcrkpPO 5I1w== X-Gm-Message-State: ALoCoQmK/BD1hAb6GXQEKsIQ3em7w16GJHE31YVeP+RS+bZozBftotG+AG3pyREdwWDgNxVQZxI7 X-Received: by 10.68.227.201 with SMTP id sc9mr11860528pbc.19.1422024577130; Fri, 23 Jan 2015 06:49:37 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id oc7sm2146455pdb.68.2015.01.23.06.49.35 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 23 Jan 2015 06:49:36 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Fri, 23 Jan 2015 08:49:21 -0600 Message-Id: <1422024563-27096-3-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1422024563-27096-1-git-send-email-greg.bellows@linaro.org> References: <1422024563-27096-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.182 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH 2/4] target-arm: Add extended RVBAR support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added RVBAR_EL2 and RVBAR_EL3 CP register support. All RVBAR_EL# registers point to the same location and only the highest EL version exists at any one time. Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- target-arm/helper.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index c9b1c08..d5f0997 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3053,17 +3053,30 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue = cpu->mvfr2 }, REGINFO_SENTINEL }; - ARMCPRegInfo rvbar = { - .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, - .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar - }; - define_one_arm_cp_reg(cpu, &rvbar); + /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ + if (!arm_feature(env, ARM_FEATURE_EL3) && + !arm_feature(env, ARM_FEATURE_EL2)) { + ARMCPRegInfo rvbar = { + .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, + .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar + }; + define_one_arm_cp_reg(cpu, &rvbar); + } define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_EL2)) { define_arm_cp_regs(cpu, v8_el2_cp_reginfo); + /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + ARMCPRegInfo rvbar = { + .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, + .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar + }; + define_one_arm_cp_reg(cpu, &rvbar); + } } else { /* If EL2 is missing but higher ELs are enabled, we need to * register the no_el2 reginfos. @@ -3074,6 +3087,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, el3_cp_reginfo); + ARMCPRegInfo rvbar = { + .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1, + .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar + }; + define_one_arm_cp_reg(cpu, &rvbar); } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new