From patchwork Wed Jan 21 18:49:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 431579 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C950F14029E for ; Thu, 22 Jan 2015 05:51:02 +1100 (AEDT) Received: from localhost ([::1]:49750 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE0Mm-0007OB-QL for incoming@patchwork.ozlabs.org; Wed, 21 Jan 2015 13:51:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50401) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE0Ly-0006BT-Pr for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:50:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YE0Lu-0001F2-2u for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:50:10 -0500 Received: from mail-pa0-f54.google.com ([209.85.220.54]:34063) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YE0Lt-0001E5-Tw for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:50:06 -0500 Received: by mail-pa0-f54.google.com with SMTP id eu11so20235961pac.13 for ; Wed, 21 Jan 2015 10:50:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LODAUk0ZucuZW3f8WST19GsgYAV+V5z8dfi08K4l/LM=; b=goaJ/lNmieacCuy2cALySXrRP/eQLcfcSUX0bkdKGW9SVLgDM4swv/4pc8waBIS5uk jhwLiSP+yNKZy01Lwxavp5AOSyv7BMOe2ixBAaYrQu5VB413fkHP0/u0IjRLs+JXiLNU rp0nXZOd1tNJjm8QmNBesyIhqCoL+9jGGNvm/Y9UFEZjtkmIYHhfv4hhd9Rb23+uYp1J FnrimX5KvjACIXErZMGuw7JyQAZj/b2A/mpMJTnBLiEr8vjdVp9LtW5C6jyUWY3Jn35A ORTJyszEt4eBW/OiY/OdIIl9u6DL/l9z6yZgl84wzCq8cc6ubTzrZQpomIBrRKXlOWfK Y9Yw== X-Gm-Message-State: ALoCoQlw8eh92YiQxcVw4lZ+YkxOfD6Rp9EnDdb/H/pBhZQe00vaIYe5fGBhZDFbtrPSKM1efnvq X-Received: by 10.68.234.134 with SMTP id ue6mr64350417pbc.47.1421866205265; Wed, 21 Jan 2015 10:50:05 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id zk9sm7047429pac.1.2015.01.21.10.50.03 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 21 Jan 2015 10:50:04 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, peter.maydell@linaro.org, christoffer.dall@linaro.org Date: Wed, 21 Jan 2015 12:49:50 -0600 Message-Id: <1421866193-24941-2-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1421866193-24941-1-git-send-email-greg.bellows@linaro.org> References: <1421866193-24941-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.54 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v2 1/4] target-arm: Add CPU property to disable AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Adds registration and get/set functions for enabling/disabling the AArch64 execution state on AArch64 CPUs. By default AArch64 execution state is enabled on AArch64 CPUs, setting the property to off, will disable the execution state. The below QEMU invocation would have AArch64 execution state disabled. $ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off Also adds stripping of features from CPU model string in acquiring the ARM CPU by name. Signed-off-by: Greg Bellows --- v1 -> v2 - Scrap the custom CPU feature parsing in favor of using the default CPU parsing. - Add registration of CPU AArch64 property to disable/enable the AArch64 feature. --- target-arm/cpu.c | 6 +++++- target-arm/cpu64.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 285947f..29ed691 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -514,13 +514,17 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; char *typename; + char *cpuname; if (!cpu_model) { return NULL; } - typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model); + cpuname = g_strdup(cpu_model); + cpuname = strtok(cpuname, ","); + typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname); oc = object_class_by_name(typename); + g_free(cpuname); g_free(typename); if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || object_class_is_abstract(oc)) { diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index bb778b3..5a59280 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -32,6 +32,11 @@ static inline void set_feature(CPUARMState *env, int feature) env->features |= 1ULL << feature; } +static inline void unset_feature(CPUARMState *env, int feature) +{ + env->features &= ~(1ULL << feature); +} + #ifndef CONFIG_USER_ONLY static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -170,8 +175,32 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = NULL } }; +static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); +} + +static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (value == false) { + unset_feature(&cpu->env, ARM_FEATURE_AARCH64); + } else { + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + } +} + static void aarch64_cpu_initfn(Object *obj) { + object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, + aarch64_cpu_set_aarch64, NULL); + object_property_set_description(obj, "aarch64", + "Set on/off to enable/disable aarch64 " + "execution state ", + NULL); } static void aarch64_cpu_finalizefn(Object *obj)