From patchwork Tue Jan 6 05:57:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 425548 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A1907140082 for ; Tue, 6 Jan 2015 17:03:40 +1100 (AEDT) Received: from localhost ([::1]:35024 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y8NEt-00032L-Ep for incoming@patchwork.ozlabs.org; Tue, 06 Jan 2015 01:03:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55340) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y8NEZ-0002ZP-Qd for qemu-devel@nongnu.org; Tue, 06 Jan 2015 01:03:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y8NEW-0007tC-KW for qemu-devel@nongnu.org; Tue, 06 Jan 2015 01:03:15 -0500 Received: from szxga03-in.huawei.com ([119.145.14.66]:60663) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y8NEV-0007np-Qs for qemu-devel@nongnu.org; Tue, 06 Jan 2015 01:03:12 -0500 Received: from 172.24.2.119 (EHLO szxeml413-hub.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id AZQ35729; Tue, 06 Jan 2015 13:59:38 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml413-hub.china.huawei.com (10.82.67.152) with Microsoft SMTP Server id 14.3.158.1; Tue, 6 Jan 2015 13:59:28 +0800 From: Shannon Zhao To: , , , , , Date: Tue, 6 Jan 2015 13:57:19 +0800 Message-ID: <1420523839-11672-4-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1420523839-11672-1-git-send-email-zhaoshenglong@huawei.com> References: <1420523839-11672-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.54AB79D3.0043, ss=1, re=0.001, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b5534252f4eaa10057f951f226188a8b X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] X-Received-From: 119.145.14.66 Cc: wanghaibin.wang@huawei.com, hangaohuai@huawei.com, peter.huangpeng@huawei.com, zhaoshenglong@huawei.com Subject: [Qemu-devel] [RFC PATCH v3 3/3] hw/arm/boot: Generate memory dtb according to NUMA topology X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a new function arm_generate_memory_dtb which is used to generate memory dtb according to NUMA topology and set the NUMA topology property of every cpu. Signed-off-by: Shannon Zhao --- hw/arm/boot.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 77 insertions(+), 3 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 52ebd8b..a39b2b4 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -312,6 +312,82 @@ static void set_kernel_args_old(const struct arm_boot_info *info) } } +/* + * arm_generate_memory_dtb() - generate memory dtb according to NUMA topology + * @fdt: the pointer to device tree + * @binfo: struct describing the boot environment + * @acells: address-cells of device tree + * @scells: size-cells of device tree + * + * Returns:0 success, + * -1 on errors. + * + */ +static int arm_generate_memory_dtb(void *fdt, const struct arm_boot_info *binfo, + uint32_t acells, uint32_t scells) +{ + CPUState *cpu; + int i = 0; + + if (!nb_numa_nodes) { + qemu_fdt_add_subnode(fdt, "/memory"); + qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); + return qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg", + acells, binfo->loader_start, + scells, binfo->ram_size); + } + + struct { + uint64_t mem_map[6]; + uint64_t cpu_map[6]; + } numa_map; + + hwaddr mem_base = binfo->loader_start; + + for (i = 0; i < nb_numa_nodes; i++) { + /* Generate mem_map */ + char *nodename; + nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); + qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", + acells, mem_base, + scells, numa_info[i].node_mem - 1); + numa_map.mem_map[0] = 0x1; + numa_map.mem_map[1] = i; + numa_map.mem_map[2] = 0x1; + numa_map.mem_map[3] = 0x0; + numa_map.mem_map[4] = 0x1; + numa_map.mem_map[5] = 0xffff; + + qemu_fdt_setprop_sized_cells_from_array(fdt, nodename, + "arm,associativity", 3, numa_map.mem_map); + + mem_base += numa_info[i].node_mem; + g_free(nodename); + + /* Generate cpu_map */ + CPU_FOREACH(cpu) { + if (test_bit(cpu->cpu_index, numa_info[i].node_cpu)) { + numa_map.cpu_map[0] = 0x1; + numa_map.cpu_map[1] = i; + numa_map.cpu_map[2] = 0x1; + numa_map.cpu_map[3] = 0x0; + numa_map.cpu_map[4] = 0x1; + numa_map.cpu_map[5] = cpu->cpu_index; + nodename = g_strdup_printf("/cpus/cpu@%d", cpu->cpu_index); + qemu_fdt_setprop_sized_cells_from_array(fdt, nodename, + "arm,associativity", 3, numa_map.cpu_map); + g_free(nodename); + } + } + } + qemu_fdt_setprop_sized_cells(fdt, "/", + "arm,associativity-reference-points", 1, 0, 1, 1); + + return 0; +} + /** * load_dtb() - load a device tree binary image into memory * @addr: the address to load the image at @@ -387,9 +463,7 @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo, goto fail; } - rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg", - acells, binfo->loader_start, - scells, binfo->ram_size); + rc = arm_generate_memory_dtb(fdt, binfo, acells, scells); if (rc < 0) { fprintf(stderr, "couldn't set /memory/reg\n"); goto fail;