From patchwork Mon Dec 15 18:51:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 421552 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 595311400D2 for ; Tue, 16 Dec 2014 05:56:44 +1100 (AEDT) Received: from localhost ([::1]:41488 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0ap0-0000Qj-C2 for incoming@patchwork.ozlabs.org; Mon, 15 Dec 2014 13:56:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0akI-0000gE-SM for qemu-devel@nongnu.org; Mon, 15 Dec 2014 13:51:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y0akC-0005w0-Vm for qemu-devel@nongnu.org; Mon, 15 Dec 2014 13:51:50 -0500 Received: from mail-pd0-f180.google.com ([209.85.192.180]:58602) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0akC-0005vq-Ak for qemu-devel@nongnu.org; Mon, 15 Dec 2014 13:51:44 -0500 Received: by mail-pd0-f180.google.com with SMTP id w10so12210723pde.11 for ; Mon, 15 Dec 2014 10:51:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l0o25fh6vWuD89rykl6Fb3QpjVhwzrKrsQ+jD8Haqn8=; b=UIh2B7VBVkKnjK9YXMwYpivdaj357wF573QWCPVYemaf5QvSA621IdJCvH81iKGDd/ 6mBsNbnn3L3lvyYRxW9+NogJCK/dW4sH1eaeN1j8QvTqiSjL+Bsdw6IAUgUPKM2jvJa+ M38oBYy7Eyt0mFvszTf+dXF99mij/XDAov5N0AdO8Q/rtSRcV0x4qpC9JGERPBAb10AJ dgv96fVFOX5U8/yaqUpRqzVQyQ2Q3KXxMMTAm6uPf5ZF8C9NXlaaSYYNxOQ5bfEttpgs ZnAp7bQJrP9iqf6AhMN1wuyCLRwwkzNmFBzcmmyK79hZ6bkqHo5IYJAyESj3EXG3yPaj DGLQ== X-Gm-Message-State: ALoCoQk4QT6NgEYwRfehXJdNmfepCEXcIz0R4eVk4KWhT+RR48Uw+uJXb89C7Gw/UpahwGhA4f3G X-Received: by 10.68.232.104 with SMTP id tn8mr53724969pbc.31.1418669503769; Mon, 15 Dec 2014 10:51:43 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id bq7sm9972513pdb.50.2014.12.15.10.51.42 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 15 Dec 2014 10:51:43 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Mon, 15 Dec 2014 12:51:13 -0600 Message-Id: <1418669479-23908-10-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1418669479-23908-1-git-send-email-greg.bellows@linaro.org> References: <1418669479-23908-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.180 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v3 09/15] target-arm: Add ARMCPU secure property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added a "has_el3" state property to the ARMCPU descriptor. This property indicates whether the ARMCPU has security extensions enabled (EL3) or not. By default it is disabled at this time. Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v1 -> v2 - Added set of has_el3 to true when EL3 is enabled v2 -> v3 - Properly init has_el3 - Fixed typo --- target-arm/cpu-qom.h | 2 ++ target-arm/cpu.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index dcfda7d..ed5a644 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -100,6 +100,8 @@ typedef struct ARMCPU { bool start_powered_off; /* CPU currently in PSCI powered-off state */ bool powered_off; + /* CPU has security extension */ + bool has_el3; /* PSCI conduit used to invoke PSCI methods * 0 - disabled, 1 - smc, 2 - hvc diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 01afed2..069e090 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -388,6 +388,9 @@ static Property arm_cpu_reset_hivecs_property = static Property arm_cpu_rvbar_property = DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); +static Property arm_cpu_has_el3_property = + DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); + static void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -407,6 +410,14 @@ static void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, &error_abort); } + + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { + /* Add the has_el3 state CPU property only if EL3 is allowed. This will + * prevent "has_el3" from existing on CPUs which cannot support EL3. + */ + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, + &error_abort); + } } static void arm_cpu_finalizefn(Object *obj) @@ -476,6 +487,18 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->reset_sctlr |= (1 << 13); } + if (!cpu->has_el3) { + /* If the has_el3 CPU property is disabled then we need to disable the + * feature. + */ + unset_feature(env, ARM_FEATURE_EL3); + + /* Disable the security extension feature bits in the processor feature + * register as well. This is id_pfr1[7:4]. + */ + cpu->id_pfr1 &= ~0xf0; + } + register_cp_regs_for_features(cpu); arm_cpu_register_gdb_regs_for_features(cpu);