From patchwork Fri Dec 12 17:47:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 420613 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1DE6514009B for ; Sat, 13 Dec 2014 04:48:11 +1100 (AEDT) Received: from localhost ([::1]:58833 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzUK1-0000iE-Ca for incoming@patchwork.ozlabs.org; Fri, 12 Dec 2014 12:48:09 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35102) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzUJd-0000NE-TT for qemu-devel@nongnu.org; Fri, 12 Dec 2014 12:47:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XzUJW-0008B7-Rx for qemu-devel@nongnu.org; Fri, 12 Dec 2014 12:47:45 -0500 Received: from mail-qc0-f171.google.com ([209.85.216.171]:59198) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzUJW-0008At-OP for qemu-devel@nongnu.org; Fri, 12 Dec 2014 12:47:38 -0500 Received: by mail-qc0-f171.google.com with SMTP id r5so5888004qcx.16 for ; Fri, 12 Dec 2014 09:47:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=5JS+wCFzOpWEyl6xXTnfA6kK5941cJEgSk4rg4jQ35U=; b=jGiC2PqSQNEkvqk0tmBs46RTMAkXCw7L6M+Q3qSmdE6GTpQxUQNC1ZzmRBSttitWDm tDFAz67l9HE+mUxO2uWw6Mb628m/4XRZEcf9ffjc8NP03ysUmHR604atM1m29Ovz/f14 96YFmPLIenF44wl8UHdI8Ns8NFTAy2fxXrL/MddMffyBphovflTln4pHsndBxSzxcpmI ypLCHmC0jp+36xvwjpAQH6cINb3dFDwbZVqA/ZJ1KrQmwumjSZ8UKTOEl1wGWizlv7GX /XZO+OtWu3pVR9Ed+VKN+EP5pwhIkqGRrgsC0MkxAKxlmX0kjVlohW9iRlIGsMTT5pu7 plQQ== X-Gm-Message-State: ALoCoQklFKYhUN1fsC6wh0nToK1SoKj8ATOOThZQXiUbkL/EmC0V0J20dAhARxEzCEYK8YtIv+Xq X-Received: by 10.229.19.3 with SMTP id y3mr33004897qca.1.1418406458250; Fri, 12 Dec 2014 09:47:38 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id 8sm1957409qgf.36.2014.12.12.09.47.37 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 12 Dec 2014 09:47:37 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Fri, 12 Dec 2014 11:47:30 -0600 Message-Id: <1418406450-14961-1-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.216.171 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH] target-arm: Merge EL3 CP15 register lists X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Merge of the v8_el2_cp_reginfo and el3_cp_reginfo ARMCPRegInfo lists. Previously, some EL3 registers were restricted to the ARMv8 list under the impression that they were not needed on ARMv7. However, this is not the case as the ARMv7/32-bit variants rely on the ARMv8/64-bit variants to handle migration and reset. For this reason they must always exist. Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- This is a fix of a regression exposed in patchset 1417637167-20640-1-git-send-email-greg.bellows@linaro.org. Apply this patch prior to applying the other patchset. --- target-arm/helper.c | 55 +++++++++++++++++++++++------------------------------ 1 file changed, 24 insertions(+), 31 deletions(-) -- 1.8.3.2 diff --git a/target-arm/helper.c b/target-arm/helper.c index 96abbed..3ef0f1f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2413,7 +2413,30 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; -static const ARMCPRegInfo v8_el3_cp_reginfo[] = { +static const ARMCPRegInfo el3_cp_reginfo[] = { + { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), + .resetvalue = 0, .writefn = scr_write }, + { .name = "SCR", .type = ARM_CP_NO_MIGRATE, + .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), + .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, + { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.sder) }, + { .name = "SDER", + .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, + /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ + { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, + .access = PL3_W | PL1_R, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, + { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, + .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0, .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write, @@ -2451,33 +2474,6 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = { REGINFO_SENTINEL }; -static const ARMCPRegInfo el3_cp_reginfo[] = { - { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, - .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), - .resetvalue = 0, .writefn = scr_write }, - { .name = "SCR", .type = ARM_CP_NO_MIGRATE, - .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, - .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), - .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, - { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, - .access = PL3_RW, .resetvalue = 0, - .fieldoffset = offsetof(CPUARMState, cp15.sder) }, - { .name = "SDER", - .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, - .access = PL3_RW, .resetvalue = 0, - .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, - /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ - { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, - .access = PL3_W | PL1_R, .resetvalue = 0, - .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, - { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, - .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, - .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, - REGINFO_SENTINEL -}; - static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri) { /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, @@ -3077,9 +3073,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } if (arm_feature(env, ARM_FEATURE_EL3)) { - if (arm_feature(env, ARM_FEATURE_V8)) { - define_arm_cp_regs(cpu, v8_el3_cp_reginfo); - } define_arm_cp_regs(cpu, el3_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_MPU)) {