From patchwork Thu Dec 11 23:29:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 420298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 434D514009B for ; Fri, 12 Dec 2014 10:34:35 +1100 (AEDT) Received: from localhost ([::1]:54673 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDFh-0003cU-4f for incoming@patchwork.ozlabs.org; Thu, 11 Dec 2014 18:34:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57600) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDBT-0004HE-4c for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:30:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XzDBN-0001Hy-Qu for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:30:10 -0500 Received: from mail-pd0-f176.google.com ([209.85.192.176]:39400) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDBN-0001Fj-F4 for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:30:05 -0500 Received: by mail-pd0-f176.google.com with SMTP id r10so3955336pdi.21 for ; Thu, 11 Dec 2014 15:30:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jfUSZv0WUTnbcNaEy0phlMExfGhSe6pTGGPaqHXzSkQ=; b=GLimsXm99WfDHAAc6tI16KmPjokhCua5KEPeoN1ZW7ab/u7I0Q3PaXrYurxYzjIajS GgavoUkXNtO9Ypaq4Gr8GRvQ/Z6jhnVRCxiCd49qnQ270urDZmURObrI4VfQaS4/nw6P jkWQXeXYtk1M1XN6RP/vwPatWO7Bg7dJn+XIOsA0altSmL6E5peCbTNWsoC9Kf4g0jQY Hy7LCdB3KtngrwXvkWVXrpH4+JuGEIuIuJpBpR7OAQ8ZOjc3PLHEscEywudozHh19/0o YHMzWpHkc5EM1imc5I+2FfwPbuYhZvi7kfAzWyQ95xAwbP5DC/NEQZFT35mFrqjg1i4W TS+w== X-Gm-Message-State: ALoCoQkRjyqzLN9BsGCOHvrCVz6NJzqbz635pA9j3Xe1boMCKVhmeGgD/jntJuG7FF90QSYPIaSv X-Received: by 10.70.92.100 with SMTP id cl4mr21235226pdb.151.1418340604893; Thu, 11 Dec 2014 15:30:04 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id ip1sm2362908pbc.0.2014.12.11.15.30.02 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Dec 2014 15:30:03 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 11 Dec 2014 17:29:29 -0600 Message-Id: <1418340569-30519-16-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1418340569-30519-1-git-send-email-greg.bellows@linaro.org> References: <1418340569-30519-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.176 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v2 15/15] target-arm: add cpu feature EL3 to CPUs with Security Extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- target-arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 758e8f8..cb89ee2 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -669,6 +669,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -757,6 +758,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -824,6 +826,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). @@ -891,6 +894,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_LPAE); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0;