From patchwork Thu Dec 11 23:29:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 420304 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 61A6B14009B for ; Fri, 12 Dec 2014 10:39:17 +1100 (AEDT) Received: from localhost ([::1]:54703 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDKF-0000gC-Iv for incoming@patchwork.ozlabs.org; Thu, 11 Dec 2014 18:39:15 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57543) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDBM-00045F-U1 for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:30:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XzDBH-00010U-03 for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:30:04 -0500 Received: from mail-pd0-f181.google.com ([209.85.192.181]:34010) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDBG-0000zH-Oy for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:29:58 -0500 Received: by mail-pd0-f181.google.com with SMTP id v10so5944332pde.40 for ; Thu, 11 Dec 2014 15:29:58 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N1zyUnE3zxhqKKU3X8ZjCiZTVlqMeTfV6tIfCal0Q6s=; b=eimgsofuCjCbPbWkcATo8bggpSe1M7WdjJWTlBwujJEF+Bl3KxBfafzSTvL+zipTZ1 1y1XT3NC3sRlCUHRcJPlZkEvH5H8IqBR/4qdqX2TcOV4aolRF3++mA2g/251P8JB1PpH kB9bk+0//7VSeJRg1kLVELV5QOxVK93m52XPygXbh+Zmn/RX2GOPQpwvzBPpjfXkKBz4 cdhYJPgapcaxC9PBWA0xlvFNbHyfNXmuK6qaKPXRfqTWbngfGQmXm0eOTiUUpSsF2vLC z8+JAtrUq8/+9voFl1JMUm7QohJYmiLaq6UDhI/6odcS2PKRpiYr8oocOpObGSY5SUy9 FIuw== X-Gm-Message-State: ALoCoQlBTMdqc1U0+HtXT2Yeyxs2SR806U88EDAZCORsiMzKdy54ZieHF737Ug/6KmarOq0od2kZ X-Received: by 10.68.137.101 with SMTP id qh5mr1858695pbb.13.1418340598144; Thu, 11 Dec 2014 15:29:58 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id ip1sm2362908pbc.0.2014.12.11.15.29.56 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Dec 2014 15:29:57 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 11 Dec 2014 17:29:25 -0600 Message-Id: <1418340569-30519-12-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1418340569-30519-1-git-send-email-greg.bellows@linaro.org> References: <1418340569-30519-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.181 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v2 11/15] target-arm: Enable CPU has_el3 prop during VE init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Adds setting of the CPU has_el3 property based on the vexpress machine secure state property during initialization. This enables/disables EL3 state during start-up. Changes include adding an additional secure state boolean during vexpress CPU initialization. Also enables the ARM secure boot by default. Signed-off-by: Greg Bellows --- v1 -> v2 - Changes CPU property name from "secure" to "has_el3" - Change conditional to handle machine state default of secure. The check now checks if the machine secure property has been disabled which causes the CPU EL3 feautre to be disabled. - Add setting of arm_boot_info.secure_boot to true --- hw/arm/vexpress.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index c82c32e..d3fb2bd 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -196,7 +196,7 @@ struct VEDBoardInfo { }; static void init_cpus(const char *cpu_model, const char *privdev, - hwaddr periphbase, qemu_irq *pic) + hwaddr periphbase, qemu_irq *pic, bool secure) { ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model); DeviceState *dev; @@ -213,6 +213,15 @@ static void init_cpus(const char *cpu_model, const char *privdev, Object *cpuobj = object_new(object_class_get_name(cpu_oc)); Error *err = NULL; + if (!secure) { + object_property_set_bool(cpuobj, false, "has_el3", &err); + if (err) { + error_report("'secure' machine property not supported " + "with %s cpu", cpu_model); + exit(1); + } + } + if (object_property_find(cpuobj, "reset-cbar", NULL)) { object_property_set_int(cpuobj, periphbase, "reset-cbar", &error_abort); @@ -288,7 +297,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms, memory_region_add_subregion(sysmem, 0x60000000, ram); /* 0x1e000000 A9MPCore (SCU) private memory region */ - init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic); + init_cpus(cpu_model, "a9mpcore_priv", 0x1e000000, pic, vms->secure); /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ @@ -374,7 +383,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms, memory_region_add_subregion(sysmem, 0x80000000, ram); /* 0x2c000000 A15MPCore private memory region (GIC) */ - init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic); + init_cpus(cpu_model, "a15mpcore_priv", 0x2c000000, pic, vms->secure); /* A15 daughterboard peripherals: */ @@ -699,6 +708,8 @@ static void vexpress_common_init(MachineState *machine) daughterboard->bootinfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; daughterboard->bootinfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; daughterboard->bootinfo.modify_dtb = vexpress_modify_dtb; + /* Indicate that when booting Linux we should be in secure state */ + daughterboard->bootinfo.secure_boot = true; arm_load_kernel(ARM_CPU(first_cpu), &daughterboard->bootinfo); }