From patchwork Thu Dec 11 23:29:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 420297 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E4DD414009B for ; Fri, 12 Dec 2014 10:33:05 +1100 (AEDT) Received: from localhost ([::1]:54660 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDEF-0000wJ-PV for incoming@patchwork.ozlabs.org; Thu, 11 Dec 2014 18:33:03 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57527) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDBL-00041w-AE for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:30:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XzDBF-0000wj-ER for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:30:03 -0500 Received: from mail-pa0-f44.google.com ([209.85.220.44]:40239) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XzDBF-0000vt-9J for qemu-devel@nongnu.org; Thu, 11 Dec 2014 18:29:57 -0500 Received: by mail-pa0-f44.google.com with SMTP id et14so6062247pad.3 for ; Thu, 11 Dec 2014 15:29:56 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hhE2Zi3xXdUlfb42nzyEOC1H9NrYUwUoX647+UXuQL8=; b=BGk7sM1tknOJlpmIu4nwQ/p2sLqgoAAl1L0Qxlag+G4w/YFmf8SwTE0vw9AjXwLt+n nIb4mwifYNHX/6wyWzPg7+NXXWXBmKLUb6BHx5+H9CGUM4/iyPvODtPRCr+fqdNr8yrv g2NSCE+ubinkWGgzFeby5GZlghWImB7zOOtN6LGKxIonmtraj5VQitMd+shOHyOESa2k OXCnY3CUgOcSjNgf3tLAskHjGY4Z8wkfnjiBDrAoZQoK1pDlTok2rKP+19EXVeHX4rMi QWhL/9tihLPy6MqyeYgNGIR4+cC0UBIHfhz1s9j+NZNZ+o7qBtph6smiq4Qbu+bsjk4S gcHQ== X-Gm-Message-State: ALoCoQltvy8yNiMq115INzYPHh5lI1tfOMUWLhRzrYdE9zPOa8oLVftLtNDobMmMOv1lXy4XG9YD X-Received: by 10.68.57.199 with SMTP id k7mr21433786pbq.25.1418340596547; Thu, 11 Dec 2014 15:29:56 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id ip1sm2362908pbc.0.2014.12.11.15.29.55 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Dec 2014 15:29:55 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 11 Dec 2014 17:29:24 -0600 Message-Id: <1418340569-30519-11-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1418340569-30519-1-git-send-email-greg.bellows@linaro.org> References: <1418340569-30519-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.44 Cc: Greg Bellows Subject: [Qemu-devel] [PATCH v2 10/15] target-arm: Add arm_boot_info secure_boot control X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Adds the secure_boot boolean field to the arm_boot_info descriptor. This fields is used to indicate whether Linux should boot into secure or non-secure state if the ARM EL3 feature is enabled. The default is to leave the CPU in an unaltered reset state. On EL3 enabled systems, the reset state is secure and can be overridden by setting the added field to false. Signed-off-by: Greg Bellows --- hw/arm/boot.c | 10 ++++++++++ include/hw/arm/arm.h | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e6a3c5b..7ec33f3 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -457,6 +457,16 @@ static void do_cpu_reset(void *opaque) env->thumb = info->entry & 1; } } else { + /* If we are booting Linux then we need to check whether we are + * booting into secure or non-secure state and adjust the state + * accordingly. Out of reset, ARM is defined to be in secure state + * (SCR.NS = 0), we change that here is non-secure boot has been + * requested. + */ + if (arm_feature(env, ARM_FEATURE_EL3) && !info->secure_boot) { + env->cp15.scr_el3 |= SCR_NS; + } + if (CPU(cpu) == first_cpu) { if (env->aarch64) { env->pc = info->loader_start; diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index cefc9e6..6659562 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -37,6 +37,10 @@ struct arm_boot_info { hwaddr gic_cpu_if_addr; int nb_cpus; int board_id; + /* ARM machines that support security extensions use this field to control + * whether Linux is booted as securei(true) or non-secure(false). + */ + bool secure_boot; int (*atag_board)(const struct arm_boot_info *info, void *p); /* multicore boards that use the default secondary core boot functions * can ignore these two function calls. If the default functions won't