From patchwork Mon Nov 17 16:47:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 411722 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EEDB61401F1 for ; Tue, 18 Nov 2014 03:53:29 +1100 (AEDT) Received: from localhost ([::1]:48873 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPYN-0001kI-S7 for incoming@patchwork.ozlabs.org; Mon, 17 Nov 2014 11:53:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59805) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTS-0001Fm-IV for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XqPTN-00078n-0s for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:22 -0500 Received: from mail-pa0-f45.google.com ([209.85.220.45]:60540) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTM-00078d-P7 for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:16 -0500 Received: by mail-pa0-f45.google.com with SMTP id lf10so22514894pab.18 for ; Mon, 17 Nov 2014 08:48:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TKYejjU0zmij8SUhYRg1lyxq+YQKKQNgmc5OCD4+CEg=; b=E99WoLW4Td4MCwtXvwhs07eCeXp6iJS3/37LP8IzHn6X1D555guq/qKiMVbqruSbyK +tFyeeBB2yVJL23jcQ4wI5lvpF7Ry1DJsnLi/nKYgKYsaeiH8HF2KXdDjzpIqCwzM6qw RZ4bosOc797fGcZ7AeTH4f+v4urh8SKEydBnjZayNZGCdEzpgare+PpSyUWazcwThE3X RWqW8aXW+8KezRJssPptHzo3VvWjEsUZxHrvyiMzDNpmgYqMJY0CSawaqQJO+LeA4VVO xIfxTgb+fblyDYGe4mKIQ8wS6xsZQLHStaVN5WW/2nBwwwCAPh874bFrgoC46Ba4ko4f klPA== X-Gm-Message-State: ALoCoQkCmCoxcaJzHboMQDtD590BYRrm6hU8HMBeEXZeBSgmJIhRHKGDFCQINwCdoitR1wqsab/j X-Received: by 10.67.4.197 with SMTP id cg5mr5335737pad.120.1416242896197; Mon, 17 Nov 2014 08:48:16 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r2sm18499056pdi.60.2014.11.17.08.48.14 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 17 Nov 2014 08:48:15 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Mon, 17 Nov 2014 10:47:37 -0600 Message-Id: <1416242878-876-6-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> References: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.45 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v11 05/26] target-arm: add CPREG secure state support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Prepare ARMCPRegInfo to support specifying two fieldoffsets per register definition. This will allow us to keep one register definition for banked registers (different offsets for secure/ non-secure world). Also added secure state tracking field and flags. This allows for identification of the register info secure state. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Removed ARM_CP_SECSTATE_TEST macro - Replaced dropped comment v7 -> v8 - Break up the fieldoffset union to avoid need for sometimes overwriting one bank when updating fieldoffset. This also removes the need for the #define short-cut introduced in v7. v6 -> v7 - Add naming for fieldoffset fields and macros for accessing. This was needed to overcome issues with the GCC-4.4 compiler. v5 -> v6 - Separate out secure CPREG flags - Add convenience macro for testing flags - Removed extraneous newline - Move add_cpreg_to_hashtable() functionality to a later commit for which it is dependent on. - Added comment explaining fieldoffset padding v4 -> v5 - Added ARM CP register secure and non-secure bank flags - Added setting of secure and non-secure flags furing registration --- target-arm/cpu.h | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6881098..dd7d229 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -993,6 +993,21 @@ enum { ARM_CP_STATE_BOTH = 2, }; +/* ARM CP register secure state flags. These flags identify security state + * attributes for a given CP register entry. + * The existence of both or neither secure and non-secure flags indicates that + * the register has both a secure and non-secure hash entry. A single one of + * these flags causes the register to only be hashed for the specified + * security state. + * Although definitions may have any combination of the S/NS bits, each + * registered entry will only have one to identify whether the entry is secure + * or non-secure. + */ +enum { + ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ + ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ +}; + /* Return true if cptype is a valid type field. This is used to try to * catch errors where the sentinel has been accidentally left off the end * of a list of registers. @@ -1127,6 +1142,8 @@ struct ARMCPRegInfo { int type; /* Access rights: PL*_[RW] */ int access; + /* Security state: ARM_CP_SECSTATE_* bits/values */ + int secure; /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the * register read/write functions, since they are passed the ARMCPRegInfo*. @@ -1136,12 +1153,27 @@ struct ARMCPRegInfo { * fieldoffset is non-zero, the reset value of the register. */ uint64_t resetvalue; - /* Offset of the field in CPUARMState for this register. This is not - * needed if either: + /* Offset of the field in CPUARMState for this register. + * + * This is not needed if either: * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs * 2. both readfn and writefn are specified */ ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ + + /* Offsets of the secure and non-secure fields in CPUARMState for the + * register if it is banked. These fields are only used during the static + * registration of a register. During hashing the bank associated + * with a given security state is copied to fieldoffset which is used from + * there on out. + * + * It is expected that register definitions use either fieldoffset or + * bank_fieldoffsets in the definition but not both. It is also expected + * that both bank offsets are set when defining a banked register. This + * use indicates that a register is banked. + */ + ptrdiff_t bank_fieldoffsets[2]; + /* Function for making any access checks for this register in addition to * those specified by the 'access' permissions bits. If NULL, no extra * checks required. The access check is performed at runtime, not at