From patchwork Mon Nov 17 16:47:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 411741 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 6181C1401F6 for ; Tue, 18 Nov 2014 04:02:47 +1100 (AEDT) Received: from localhost ([::1]:48968 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPhN-0001pL-HY for incoming@patchwork.ozlabs.org; Mon, 17 Nov 2014 12:02:45 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60184) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPU7-0002Uz-LD for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:49:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XqPTv-0007Hz-ES for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:49:03 -0500 Received: from mail-pa0-f49.google.com ([209.85.220.49]:35342) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTt-0007Gt-Dk for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:51 -0500 Received: by mail-pa0-f49.google.com with SMTP id eu11so813507pac.22 for ; Mon, 17 Nov 2014 08:48:49 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4LemLHXS/OWHZnZcK6he6ek8sOwvzUvqbh4a26T5PrE=; b=OH4r19KVbioWSoo5bPI/MHRCtV2+vFEICK2cP5XP11xfXJHRY/lATtyzysLsAQWkpO z0bPJfWHLCJXn2IYr1MGMTgv59ElSCDX6h6motfx/3Q9HhaieBaG6rncI9XhqM1KTTid XkMDtk1cANkzje/dEFjvJqM85GAbZRUwg5LffRZFEyTDLWCP1nZAM08ffQ0EK1CB8+OS NRuxzApVbYfNUMAgijLg800MBvtXFaJ+ojQTb4Nd3crzgUdCL7X92RO9u8fMYy4/yxwl x+kHdPecx8f3DlIjiIyKA35RvihyLPvmCJ/lAWCXuUmDx2o31CRgk3UZhRzoBUDeuz7u h8ag== X-Gm-Message-State: ALoCoQl8mJGMCuYPkzrg+tq9eGRy1euUzJd4M685OEmSFRJLTH6fPJ5wiW3Tn6LFFhRu0pQsSwbl X-Received: by 10.66.150.164 with SMTP id uj4mr30948491pab.14.1416242928951; Mon, 17 Nov 2014 08:48:48 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r2sm18499056pdi.60.2014.11.17.08.48.47 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 17 Nov 2014 08:48:48 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Mon, 17 Nov 2014 10:47:58 -0600 Message-Id: <1416242878-876-27-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> References: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.49 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v11 26/26] target-arm: add cpu feature EL3 to CPUs with Security Extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index d3db279..1871865 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -640,6 +640,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -728,6 +729,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -795,6 +797,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). @@ -862,6 +865,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_LPAE); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0;