From patchwork Mon Nov 17 16:47:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 411736 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id DBA491401EB for ; Tue, 18 Nov 2014 03:59:36 +1100 (AEDT) Received: from localhost ([::1]:48932 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPeI-00054H-Qf for incoming@patchwork.ozlabs.org; Mon, 17 Nov 2014 11:59:34 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTb-0001b7-L3 for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XqPTW-0007CF-OG for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:31 -0500 Received: from mail-pa0-f53.google.com ([209.85.220.53]:43693) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTW-0007CB-Jm for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:26 -0500 Received: by mail-pa0-f53.google.com with SMTP id kq14so3661073pab.40 for ; Mon, 17 Nov 2014 08:48:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iwwi0ehsdjvfMpNiN8fhYo0L6CliQoOVJkTPUYGoNkU=; b=C2odedII+jfKEDp1JoQLwWVrtwlBcZzvWE+W63M1BhJ8KGJ0tmcjsYj57VbrN89uvY kLwPUc/f6OG4tEzIhIKwMuW47tPWc3zOi0ZtugFJNiu/82Xdroioq6Cp6lhBNeOkxj2l Y4Yy2AY2B4ihaZ7D4s0kxkXG/AbAee0VYlUhZp+0DXsTbl+byQPyivQp6IDFECQxuBQ3 sppII3Stj/tJDTVB6Qh4widnaxZQ3KSft0Rb3Dnk8jRSoHHjC40N3pTvYCj3G6F3iTdL TJNVoudNdhPTODYPtd/kNFRigKkz2e5vqnVguJ2GLVwHkFj4S5cQ4TYznzkKxh2G+oZ9 F8fQ== X-Gm-Message-State: ALoCoQnYg8p0KZeKuNeQTg2ZaQr3eUZgViZBH/bEymkgVi+RznsQKNXr1LdkVe6n0u4cdRUFbL8W X-Received: by 10.68.174.131 with SMTP id bs3mr30644861pbc.20.1416242905985; Mon, 17 Nov 2014 08:48:25 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r2sm18499056pdi.60.2014.11.17.08.48.24 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 17 Nov 2014 08:48:25 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Mon, 17 Nov 2014 10:47:43 -0600 Message-Id: <1416242878-876-12-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> References: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.53 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v11 11/26] target-arm: add SDER definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added CP register defintions for SDER and SDER32_EL3 as well as cp15.sder for register storage. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Fixed declaration order of the SDER register components v7 -> v8 - Added SDER32_EL3 register definition - Changed sder name from c1_sder to sder - Changed sder from uint32_t to uint64_t. --- target-arm/cpu.h | 1 + target-arm/helper.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2afe93a..12bd6ec 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 691bb8e..284f255 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2344,6 +2344,14 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, + { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.sder) }, + { .name = "SDER", + .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) }, /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, .access = PL3_W | PL1_R, .resetvalue = 0,