From patchwork Mon Nov 17 16:47:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 411723 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CD7661401EB for ; Tue, 18 Nov 2014 03:53:39 +1100 (AEDT) Received: from localhost ([::1]:48876 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPYY-0002AQ-3k for incoming@patchwork.ozlabs.org; Mon, 17 Nov 2014 11:53:38 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59878) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTZ-0001ZK-LO for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XqPTU-0007BY-Rz for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:29 -0500 Received: from mail-pd0-f172.google.com ([209.85.192.172]:46074) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XqPTU-0007BU-NI for qemu-devel@nongnu.org; Mon, 17 Nov 2014 11:48:24 -0500 Received: by mail-pd0-f172.google.com with SMTP id r10so21538110pdi.31 for ; Mon, 17 Nov 2014 08:48:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SPAC4IqBcKhNt6PVnBClGFSDuHlIBSJEXBHF1XhXoiY=; b=fOFB+gPBcLIoIP3+brWw/dV8ZZBRDlOTsYVtz2jbaTlyyUN8NVeppF39eKv4nn51Xq rjklMytSWeqwbok1sWiW/yuyZy4Kb2Sfz6T7atPj4j6RBEIcNRzESYBMLBdDduIhT1wV d+WSYefok7H8dmgXwHE802fQCMhu/zpR14xY4cj0VjIg0V0U6UmVrYZUgsFNGsFiowkI bmSuQt/RrTE2hY4fKgstsqul8ONU5YCqsonZ/Bn8Z3osQzX1XZUkmRxGlUFb/ys/wSQx XWWIddUmsD3+z9mM4iR/9WLwjNYA4G1JnFg5hpRSGT+wyVdGwGR9VynaDGg1+B6A0EYJ A6Ng== X-Gm-Message-State: ALoCoQk1kZ0Moxsuw6G7vPiYayKAWQcBj5xfmtpjhJO6TqCcvw+rDKvUM71i1l/pww0EeSfxsTFw X-Received: by 10.68.221.162 with SMTP id qf2mr4768215pbc.148.1416242904254; Mon, 17 Nov 2014 08:48:24 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id r2sm18499056pdi.60.2014.11.17.08.48.22 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 17 Nov 2014 08:48:23 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Mon, 17 Nov 2014 10:47:42 -0600 Message-Id: <1416242878-876-11-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> References: <1416242878-876-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.172 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v11 10/26] target-arm: add NSACR register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Implements NSACR register with corresponding read/write functions for ARMv7 and ARMv8. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Removed unused NSACR constants - Added TODO for trapping secure EL1 accesses to NSACR - Change NSACR access from PL3_RW to PL3_W - Fixed declaration order of the NSACR register components v7 -> v8 - Update naming from c1_nsacr to nsacr to match other registers being changed. - Remove NSACR read/write functions v4 -> v5 - Changed to use renamed arm_current_el() --- target-arm/cpu.h | 1 + target-arm/helper.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 532f698..2afe93a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint32_t nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ uint64_t c2_control; /* MMU translation table base control. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 8651bbc..691bb8e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2344,6 +2344,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), .resetfn = arm_cp_reset_ignore, .writefn = scr_write }, + /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ + { .name = "NSACR", .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2, + .access = PL3_W | PL1_R, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, REGINFO_SENTINEL };