From patchwork Thu Nov 6 15:50:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407605 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47B6C1400A6 for ; Fri, 7 Nov 2014 02:57:02 +1100 (AEDT) Received: from localhost ([::1]:54604 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPQi-0002AX-Fv for incoming@patchwork.ozlabs.org; Thu, 06 Nov 2014 10:57:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36663) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLc-0001d1-Ep for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPLX-00046K-5S for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:44 -0500 Received: from mail-pa0-f54.google.com ([209.85.220.54]:56909) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLW-00045U-U5 for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:39 -0500 Received: by mail-pa0-f54.google.com with SMTP id rd3so1486883pab.27 for ; Thu, 06 Nov 2014 07:51:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QATMi+yOerRMlSgMH9+scOEqfL5XgHVWHFsI9fm1dBU=; b=QlcR8tWMcBackwwp+EGoQCuM9jdHT5EoNpnk/JuJnVieqikXxYI+lqxEHCStseBi3k 4/M83Tu751vKHmbZRZxjPz4iBSmzuL/1IAMeNyT0NCJAFhuU8Z7aHCH4I4SGNjG5VLsm 7S+f9UIL6RxxSzfNTj9XJ5oe/U29DUW4NEI+JvLcTsMaCz/73V52AcokSma8SVP8wzDG IpGcEt3hYluykD8NyiCh4uRgNlEKP8F59K4hXFwzCjLrWuikLXyqRJ2EhD0I0Nw1+kpd GX/41en6ouLnfC5S0DoQ8qDlv5DXmWcggiIJRVIqU1tNwtPaupP+AAWIcZBqZcQ5ckcJ rOQA== X-Gm-Message-State: ALoCoQmMA7X2sw6Y3fdB3ekHPsLOI6oVnATBVTg01p+hfw90HOPQBwwAVgdsSNBLZacT9uggsOJP X-Received: by 10.66.139.106 with SMTP id qx10mr5419362pab.138.1415289098260; Thu, 06 Nov 2014 07:51:38 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id z9sm6245585pdp.73.2014.11.06.07.51.36 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:51:37 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 6 Nov 2014 09:50:54 -0600 Message-Id: <1415289073-14681-8-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.54 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v10 07/26] target-arm: insert AArch32 cpregs twice into hashtable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler Prepare for cp register banking by inserting every cp register twice, once for secure world and once for non-secure world. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Fixed setting of secure field in add_cpreg_to_hashtable so it uses secstate and happens in all cases. - Fixed check for disabling of migration to only occur on duplicately defined reginfos. - Fixed comment on disabling migration and reset and eliminated crn special case. - Reworked define_one_arm_cp_reg_with_opaque() secure case handling. v7 -> v8 - Updated define registers asserts to allow either a non-zero fieldoffset or non-zero bank_fieldoffsets. - Updated CP register hashing to always set the register fieldoffset when banked register offsets are specified. v5 -> v6 - Fixed NS-bit number in the CPREG hash lookup from 27 to 29. - Switched to dedicated CPREG secure flags. - Fixed disablement of reset and migration of common 32/64-bit registers. - Globally replace Aarch# with AArch# v4 -> v5 - Added use of ARM CP secure/non-secure bank flags during register processing in define_one_arm_cp_reg_with_opaque(). We now only register the specified bank if only one flag is specified, otherwise we register both a secure and non-secure instance. --- target-arm/helper.c | 98 +++++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 81 insertions(+), 17 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 1aadb79..0471e6c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3296,23 +3296,59 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, uint32_t *key = g_new(uint32_t, 1); ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; - int ns = (r->secure & ARM_CP_SECSTATE_NS) ? 1 : 0; - if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) { - /* The AArch32 view of a shared register sees the lower 32 bits - * of a 64 bit backing field. It is not migratable as the AArch64 - * view handles that. AArch64 also handles reset. - * We assume it is a cp15 register if the .cp field is left unset. + int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; + + /* Reset the secure state to the specific incoming state. This is + * necessary as the register may have been defined with both states. + */ + r2->secure = secstate; + + if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + /* Register is banked (using both entries in array). + * Overwriting fieldoffset as the array is only used to define + * banked registers but later only fieldoffset is used. */ - if (r2->cp == 0) { - r2->cp = 15; + r2->fieldoffset = r->bank_fieldoffsets[ns]; + } + + if (state == ARM_CP_STATE_AA32) { + if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + /* If the register is banked then we don't need to migrate or + * reset the 32-bit instance in certain cases: + * + * 1) If the register has both 32-bit and 64-bit instances then we + * can count on the 64-bit instance taking care of the + * non-secure bank. + * 2) If ARMv8 is enabled then we can count on a 64-bit version + * taking care of the secure bank. This requires that separate + * 32 and 64-bit definitions are provided. + */ + if ((r->state == ARM_CP_STATE_BOTH && ns) || + (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { + r2->type |= ARM_CP_NO_MIGRATE; + r2->resetfn = arm_cp_reset_ignore; + } + } else if ((secstate != r->secure) && !ns) { + /* The register is not banked so we only want to allow migration of + * the non-secure instance. + */ + r2->type |= ARM_CP_NO_MIGRATE; + r2->resetfn = arm_cp_reset_ignore; } - r2->type |= ARM_CP_NO_MIGRATE; - r2->resetfn = arm_cp_reset_ignore; + + if (r->state == ARM_CP_STATE_BOTH) { + /* We assume it is a cp15 register if the .cp field is left unset. + */ + if (r2->cp == 0) { + r2->cp = 15; + } + #ifdef HOST_WORDS_BIGENDIAN - if (r2->fieldoffset) { - r2->fieldoffset += sizeof(uint32_t); - } + if (r2->fieldoffset) { + r2->fieldoffset += sizeof(uint32_t); + } #endif + } } if (state == ARM_CP_STATE_AA64) { /* To allow abbreviation of ARMCPRegInfo @@ -3461,10 +3497,14 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, */ if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { if (r->access & PL3_R) { - assert(r->fieldoffset || r->readfn); + assert((r->fieldoffset || + (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || + r->readfn); } if (r->access & PL3_W) { - assert(r->fieldoffset || r->writefn); + assert((r->fieldoffset || + (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || + r->writefn); } } /* Bad type field probably means missing sentinel at end of reg list */ @@ -3477,8 +3517,32 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state != state && r->state != ARM_CP_STATE_BOTH) { continue; } - add_cpreg_to_hashtable(cpu, r, opaque, state, - ARM_CP_SECSTATE_NS, crm, opc1, opc2); + if (state == ARM_CP_STATE_AA32) { + /* Under AArch32 CP registers can be common + * (same for secure and non-secure world) or banked. + */ + switch (r->secure) { + case ARM_CP_SECSTATE_S: + case ARM_CP_SECSTATE_NS: + add_cpreg_to_hashtable(cpu, r, opaque, state, + r->secure, crm, opc1, opc2); + break; + default: + add_cpreg_to_hashtable(cpu, r, opaque, state, + ARM_CP_SECSTATE_S, + crm, opc1, opc2); + add_cpreg_to_hashtable(cpu, r, opaque, state, + ARM_CP_SECSTATE_NS, + crm, opc1, opc2); + break; + } + } else { + /* AArch64 registers get mapped to non-secure instance + * of AArch32 */ + add_cpreg_to_hashtable(cpu, r, opaque, state, + ARM_CP_SECSTATE_NS, + crm, opc1, opc2); + } } } }