From patchwork Thu Nov 6 15:50:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407599 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D63321400A6 for ; Fri, 7 Nov 2014 02:54:23 +1100 (AEDT) Received: from localhost ([::1]:54579 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPOA-0006GT-3O for incoming@patchwork.ozlabs.org; Thu, 06 Nov 2014 10:54:22 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36579) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLT-0001SC-BR for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPLO-0003vE-H5 for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:35 -0500 Received: from mail-pa0-f43.google.com ([209.85.220.43]:58588) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLO-0003v6-AS for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:51:30 -0500 Received: by mail-pa0-f43.google.com with SMTP id eu11so1478083pac.30 for ; Thu, 06 Nov 2014 07:51:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ux6gUU9S2fNvZCuFXF1X4gIxvNEIhOF8jkej4kFp8e0=; b=jixq09b6hMXrdfk3lHqBSVJLyQUqXHlFLQgg2oMLmYLE4VLH2jKI0H09tDoKyiM7RY XcxmueVQZkMBB4tpQPy9Dfw8cvarHjWOuX2b8DsoKRrCxdnPqpjOAoOCUD61zTJwRq+O zxg+6O+W9Cwmsy/KJIeIopp54ZGlfUPjPU+Vz8clLsqmkdPB5YYgA1/XkF9JPOmLr6Xv Fnte27tdk56pHlusIGKtoSwAWkAr3ojuFFF4evxoPmoBrVGJmvnb1WI/9F6uvABgmATs W+E6we+WllGKt1P13fhrbnKITaFbOpiMLTvFnDe2bCiMNa/x3JQ1Erg2hHjKr09bdGWT K25w== X-Gm-Message-State: ALoCoQkOeJYaPZFsfAeXgLpsw3idXD2dNQMlFEAu2/CMYF6NjRiah8xeQsY2l67rZq8ce/MeO9y8 X-Received: by 10.68.250.131 with SMTP id zc3mr5343300pbc.34.1415289089680; Thu, 06 Nov 2014 07:51:29 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id z9sm6245585pdp.73.2014.11.06.07.51.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:51:28 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 6 Nov 2014 09:50:50 -0600 Message-Id: <1415289073-14681-4-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.43 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v10 03/26] target-arm: add banked register accessors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler If EL3 is in AArch32 state certain cp registers are banked (secure and non-secure instance). When reading or writing to coprocessor registers the following macros can be used. - A32_BANKED macros are used for choosing the banked register based on provided input security argument. This macro is used to choose the bank during translation of MRC/MCR instructions that are dependent on something other than the current secure state. - A32_BANKED_CURRENT macros are used for choosing the banked register based on current secure state. This is NOT to be used for choosing the bank used during translation as it breaks monitor mode. If EL3 is operating in AArch64 state coprocessor registers are not banked anymore. The macros use the non-secure instance (_ns) in this case, which is architecturally mapped to the AArch64 EL register. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v7 -> v8 - Move use_secure_reg() function to the TBFLAG patch. v5 -> v6 - Converted macro USE_SECURE_REG() into inlince function use_secure_reg() - Globally replace Aarch# with AArch# v4 -> v5 - Cleaned-up macros to try and alleviate misuse. Made A32_BANKED macros take secure arg indicator rather than relying on USE_SECURE_REG. Incorporated the A32_BANKED macros into the A32_BANKED_CURRENT. CURRENT is now the only one that automatically chooses based on current secure state. --- target-arm/cpu.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cf30b2a..7769ccf 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -817,6 +817,33 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el) return arm_feature(env, ARM_FEATURE_AARCH64); } +/* Macros for accessing a specified CP register bank */ +#define A32_BANKED_REG_GET(_env, _regname, _secure) \ + ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns) + +#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \ + do { \ + if (_secure) { \ + (_env)->cp15._regname##_s = (_val); \ + } else { \ + (_env)->cp15._regname##_ns = (_val); \ + } \ + } while (0) + +/* Macros for automatically accessing a specific CP register bank depending on + * the current secure state of the system. These macros are not intended for + * supporting instruction translation reads/writes as these are dependent + * solely on the SCR.NS bit and not the mode. + */ +#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \ + A32_BANKED_REG_GET((_env), _regname, \ + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env)))) + +#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \ + A32_BANKED_REG_SET((_env), _regname, \ + ((!arm_el_is_aa64((_env), 3) && arm_is_secure(_env))), \ + (_val)) + void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx);