From patchwork Thu Nov 6 15:51:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407623 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id B685C1400AB for ; Fri, 7 Nov 2014 03:06:14 +1100 (AEDT) Received: from localhost ([::1]:54688 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPZc-0000MW-OZ for incoming@patchwork.ozlabs.org; Thu, 06 Nov 2014 11:06:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPMF-0002la-JX for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPM9-0004Rh-Mr for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:23 -0500 Received: from mail-pa0-f44.google.com ([209.85.220.44]:43331) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPM9-0004RU-IB for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:17 -0500 Received: by mail-pa0-f44.google.com with SMTP id bj1so1509985pad.3 for ; Thu, 06 Nov 2014 07:52:17 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DywKlWGeRhN4f7Exa3zsB1u/BF59KlhTgWsGSUkCfZk=; b=PR54W9SdZsIAzvToZ2brVaRbo0bM6GDzdk6Hf2uskeKr3lujE+Lfkc/ug1sQGbzZOy sY/o97+1BaVNIkOP4EL1Txl3DBCSFGTwJ73iNDq3WqRvk+o9X6BQjqMyfcwF0zPCDcv7 pbtKBZ4LD3EetvFQSAccw203KViwBS5BMe+nCcJmjbq87VWKdRUFiQvUTtyYT1w5qXYA 4xdpNtQKRYKTpZOttTrb4zLCCwrqLbj9ZxDW16ggCEKeJt1lF5GGMr5Ob6B116Q64hGr lm60+7D+TV612LHjlu4owMXN4xH57xlZNx3O9f8G8SOt+DXKxmjde+c22+2F8SQl3CGH 1Ezw== X-Gm-Message-State: ALoCoQkHqNWqWz4T+3TiwUmUGBd+nZMgA1oVFQ4O5JqjiYAegpUVsVpJM5nw/QD+8M0O/ofaj16D X-Received: by 10.68.192.1 with SMTP id hc1mr5057250pbc.87.1415289136955; Thu, 06 Nov 2014 07:52:16 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id z9sm6245585pdp.73.2014.11.06.07.52.14 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:52:16 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 6 Nov 2014 09:51:12 -0600 Message-Id: <1415289073-14681-26-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.44 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v10 25/26] target-arm: make MAIR0/1 banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Added endianness support to the MAIR field structure definition. v5 -> v6 - Changed _el field variants to be array based --- target-arm/cpu.h | 21 ++++++++++++++++++++- target-arm/helper.c | 12 +++++++++--- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index dd0dee0..7960a3a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -296,7 +296,26 @@ typedef struct CPUARMState { uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ - uint64_t mair_el1; + union { /* Memory attribute redirection */ + struct { +#ifdef HOST_WORDS_BIGENDIAN + uint64_t _unused_mair_0; + uint32_t mair1_ns; + uint32_t mair0_ns; + uint64_t _unused_mair_1; + uint32_t mair1_s; + uint32_t mair0_s; +#else + uint64_t _unused_mair_0; + uint32_t mair0_ns; + uint32_t mair1_ns; + uint64_t _unused_mair_1; + uint32_t mair0_s; + uint32_t mair1_s; +#endif + }; + uint64_t mair_el[4]; + }; union { /* vector base address register */ struct { uint64_t _unused_vbar; diff --git a/target-arm/helper.c b/target-arm/helper.c index 0b5330d..9faecca 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -965,20 +965,26 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { */ { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1), + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue = 0 }, /* For non-long-descriptor page tables these are PRRR and NMRR; * regardless they still act as reads-as-written for QEMU. * The override is necessary because of the overly-broad TLB_LOCKDOWN * definition. */ + /* MAIR0/1 are defined seperately from their 64-bit counterpart which + * allows them to assign the correct fieldoffset based on the endianness + * handled in the field definitions. + */ { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s), + offsetof(CPUARMState, cp15.mair0_ns) }, .resetfn = arm_cp_reset_ignore }, { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE, .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1), + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s), + offsetof(CPUARMState, cp15.mair1_ns) }, .resetfn = arm_cp_reset_ignore }, { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,