From patchwork Thu Nov 6 15:51:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407626 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CFFCE14008C for ; Fri, 7 Nov 2014 03:09:33 +1100 (AEDT) Received: from localhost ([::1]:54721 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPcp-0005Wx-T8 for incoming@patchwork.ozlabs.org; Thu, 06 Nov 2014 11:09:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36951) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPM9-0002YP-7F for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPM3-0004QH-NK for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:17 -0500 Received: from mail-pa0-f54.google.com ([209.85.220.54]:42124) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPM3-0004Pj-9p for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:11 -0500 Received: by mail-pa0-f54.google.com with SMTP id rd3so1487664pab.27 for ; Thu, 06 Nov 2014 07:52:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z+bl2WBemwhq7Bm+eEOrn/3EXYBqGLkShUJBZgvUYgE=; b=cOQFqiySdp6av+LZFeyUtWfOM8TK8mLpiOFxOyeaBzFtucU/IcrvugeZbufscfMBiO RfkDdy+UFDrCbm+2ldA4yrfRleRPOpdMinuZRUx5OTZB4bHxIrNQdp+sF0XoAt0kkR3z pOWvsW2vilq7h+OgVYAzCGEAGwSaEH3rotOnlciaXB0Hu6oS1FCdpxBggn8Lavbh+Ps9 G0hzPbZCzp4X7pyOuWrtKVJdWha10xHmLt1preuYO/hIkHlGMcJNmvMIQ/0pZKW+fqVt 7YSwWMwT5NYZsawNABRfL22YF2iop7let/XknY70BSKV9P+kpEgJ1f7ir5kQso6XKMkm MHZg== X-Gm-Message-State: ALoCoQnSd7hX6iLhPhVgVUqjZGrS3WqnBmlCMUCrW1ps3rax/TuEw80cZQmzIdWUfWIDMBdFxlv8 X-Received: by 10.70.4.164 with SMTP id l4mr5010648pdl.137.1415289130619; Thu, 06 Nov 2014 07:52:10 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id z9sm6245585pdp.73.2014.11.06.07.52.08 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:52:09 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 6 Nov 2014 09:51:09 -0600 Message-Id: <1415289073-14681-23-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.54 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v10 22/26] target-arm: make PAR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler When EL3 is running in AArch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Cleaned-up ats_write() to only call A32_BANKED_CURRENT_REG_SET() once at the endof the function. - Revert unnecessary CPreg definition changes v5 -> v6 - Changed _el field variants to be array based v3 -> v4 - Fix par union/structure definition --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 23 +++++++++++++---------- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 9518fc7..4ddfe77 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -279,7 +279,15 @@ typedef struct CPUARMState { }; uint64_t far_el[4]; }; - uint64_t par_el1; /* Translation result. */ + union { /* Translation result. */ + struct { + uint64_t _unused_par_0; + uint64_t par_ns; + uint64_t _unused_par_1; + uint64_t par_s; + }; + uint64_t par_el[4]; + }; uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint64_t c9_pmcr; /* performance monitor control register */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 6296731..67cb649 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1404,6 +1404,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) int prot; int ret, is_user = ri->opc2 & 2; int access_type = ri->opc2 & 1; + uint64_t par64; ret = get_phys_addr(env, value, access_type, is_user, &phys_addr, &prot, &page_size); @@ -1412,7 +1413,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) * translation table format, but with WnR always clear. * Convert it to a 64-bit PAR. */ - uint64_t par64 = (1 << 11); /* LPAE bit always set */ + par64 = (1 << 11); /* LPAE bit always set */ if (ret == 0) { par64 |= phys_addr & ~0xfffULL; /* We don't set the ATTR or SH fields in the PAR. */ @@ -1424,7 +1425,6 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) * fault. */ } - env->cp15.par_el1 = par64; } else { /* ret is a DFSR/IFSR value for the short descriptor * translation table format (with WnR always clear). @@ -1434,23 +1434,25 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) /* We do not set any attribute bits in the PAR */ if (page_size == (1 << 24) && arm_feature(env, ARM_FEATURE_V7)) { - env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1; + par64 = (phys_addr & 0xff000000) | (1 << 1); } else { - env->cp15.par_el1 = phys_addr & 0xfffff000; + par64 = phys_addr & 0xfffff000; } } else { - env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) | - ((ret & (1 << 12)) >> 6) | - ((ret & 0xf) << 1) | 1; + par64 = ((ret & (1 << 10)) >> 5) | ((ret & (1 << 12)) >> 6) | + ((ret & 0xf) << 1) | 1; } } + + A32_BANKED_CURRENT_REG_SET(env, par, par64); } #endif static const ARMCPRegInfo vapa_cp_reginfo[] = { { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .resetvalue = 0, - .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1), + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s), + offsetoflow32(CPUARMState, cp15.par_ns) }, .writefn = par_write }, #ifndef CONFIG_USER_ONLY { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, @@ -1903,8 +1905,9 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 }, { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0, - .access = PL1_RW, .type = ARM_CP_64BIT, - .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 }, + .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s), + offsetof(CPUARMState, cp15.par_ns)} }, { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0, .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),