From patchwork Thu Nov 6 15:51:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Bellows X-Patchwork-Id: 407620 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id EBBA214008C for ; Fri, 7 Nov 2014 03:04:08 +1100 (AEDT) Received: from localhost ([::1]:54668 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPXa-0005Vz-Mt for incoming@patchwork.ozlabs.org; Thu, 06 Nov 2014 11:04:06 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36900) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPM2-0002M5-77 for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XmPLw-0004Np-Uh for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:10 -0500 Received: from mail-pa0-f54.google.com ([209.85.220.54]:41531) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XmPLw-0004Nf-IF for qemu-devel@nongnu.org; Thu, 06 Nov 2014 10:52:04 -0500 Received: by mail-pa0-f54.google.com with SMTP id rd3so1498876pab.13 for ; Thu, 06 Nov 2014 07:52:04 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fysWPs2HGYoCj8x3YPjgnQznDl//FVrwU9GneAVWHaE=; b=NtWwI2IHoMYN2zH2ZvHts1fvx3r8tyFegP4oMZ1W+21wA4/fvwfbiFBFIiMUmBvtM1 6kB463kOZz80p+OTpLmNQvzYJPgHUbWLoTKKo8hJ6dQ/hChgYtC0iSfL0C8nNzl/w0CS HypZjBg3zYV/YsZKD7PwEQxIS4JsukmlKGumIYLz5nBFXFZqBZ6/mtbceVVfdEooFJwR 60zu8XxiMeH61J3skvItaQf8fq+RM4eu3zPqvNosRAKAQw+xvzP+ep3yp38WRwE2O5iX QougDgBCeXdE4ddu6hKmqkWV3Bs7OBkHirvZgerOuK0qaQoXQWeqC2wypbJizQtFCNZz upjQ== X-Gm-Message-State: ALoCoQnXrmPw0iGcHR0hmO1N6VnBNg3xHeDhtq/j5rJDcFnOkg10+HtkeHnzAPdIHcSZq9DUiZJN X-Received: by 10.68.219.70 with SMTP id pm6mr5222015pbc.43.1415289123952; Thu, 06 Nov 2014 07:52:03 -0800 (PST) Received: from gbellows-linaro.qualcomm.com (rrcs-67-52-129-61.west.biz.rr.com. [67.52.129.61]) by mx.google.com with ESMTPSA id z9sm6245585pdp.73.2014.11.06.07.52.01 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Nov 2014 07:52:03 -0800 (PST) From: Greg Bellows To: qemu-devel@nongnu.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch, peter.maydell@linaro.org Date: Thu, 6 Nov 2014 09:51:06 -0600 Message-Id: <1415289073-14681-20-git-send-email-greg.bellows@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> References: <1415289073-14681-1-git-send-email-greg.bellows@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.54 Cc: greg.bellows@linaro.org Subject: [Qemu-devel] [PATCH v10 19/26] target-arm: make IFSR banked X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Fabian Aggeler When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and storage. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell --- v8 -> v9 - Added definition for IFSR32_EL2 - Changed ifsr cp15 fields to uint64_t --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 13 +++++++++---- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0609ccc..c271ab2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -242,7 +242,15 @@ typedef struct CPUARMState { uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ uint64_t scr_el3; /* Secure configuration register. */ - uint32_t ifsr_el2; /* Fault status registers. */ + union { /* Fault status registers. */ + struct { + uint64_t ifsr_ns; + uint64_t ifsr_s; + }; + struct { + uint64_t ifsr32_el2; + }; + }; uint64_t esr_el[4]; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el[4]; /* Fault address registers. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index dbfa6bb..f47748b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1654,8 +1654,9 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]), .resetfn = arm_cp_reset_ignore, }, { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, - .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, }, + .access = PL1_RW, .resetvalue = 0, + .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s), + offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, .access = PL1_RW, @@ -2347,6 +2348,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .type = ARM_CP_NO_MIGRATE, .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, + { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1, + .access = PL2_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) }, { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, @@ -4324,11 +4329,11 @@ void arm_cpu_do_interrupt(CPUState *cs) env->exception.fsr = 2; /* Fall through to prefetch abort. */ case EXCP_PREFETCH_ABORT: - env->cp15.ifsr_el2 = env->exception.fsr; + A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", - env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress); + env->exception.fsr, (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; addr = 0x0c; mask = CPSR_A | CPSR_I;